Abstract: Some embodiments relate to a method and a corresponding apparatus for estimating the wear of a non-volatile memory. Such a method may include determining a load profile with respect to a real access load occurring during a defined test period where the load profile indicates a respectively associated access load for accesses to a first NVM, and generating access data representing the determined load profile. The method further includes determining an estimated value for the wear of a particular second NVM in part on the basis of the access data.

Abstract: The invention relates to a soft input decoding method and a decoder for generalized concatenated (GC) codes. The GC codes are constructed from inner nested block codes, such as binary Bose-Chaudhuri-Hocquenghem, BCH, codes and outer codes, such as Reed-Solomon, RS, codes. In order to enable soft input decoding for the inner block codes, a sequential stack decoding algorithm is used. Ordinary stack decoding of binary block codes requires the complete trellis of the code. In one aspect, the present invention applies instead a representation of the block codes based on the trellises of supercodes in order to reduce the memory requirements for the representation of the inner codes. This enables an efficient hardware implementation. In another aspect, the present invention provides a soft input decoding method and device employing a sequential stack decoding algorithm in combination with list-of-two decoding which is particularly well suited for applications that require very low residual error rates.

Abstract: Field error correction coding is particularly suitable for applications in non-volatile flash memories. We describe a method for error correction encoding of data to be stored in a memory device, a corresponding method for decoding a codeword matrix resulting from the encoding method, a coding device, and a computer program for performing the methods on the coding device, using a new construction for high-rate generalized concatenated (GC) codes. The codes, which are well suited for error correction in flash memories for high reliability data storage, are constructed from inner nested binary Bose-Chaudhuri-Hocquenghem (BCH) codes and outer codes, preferably Reed-Solomon (RS) codes. For the inner codes extended BCH codes are used, where only single parity-check codes are applied in the first level of the GC code. This enables high-rate codes.

Abstract: Some embodiments relate to a method and a corresponding apparatus for estimating the wear of a non-volatile memory. Such a method may include determining a load profile with respect to a real access load occurring during a defined test period where the load profile indicates a respectively associated access load for accesses to a first NVM, and generating access data representing the determined load profile. The method further includes determining an estimated value for the wear of a particular second NVM in part on the basis of the access data.

Abstract: Various embodiments are related to non-volatile memories, systems, and methods of using such. Some such embodiments include a memory controller that is configured to reserve a predetermined amount of unused dedicated memory in the NVM and control the memory system to operate in a normal mode of operation in which it is configured to provide at least write access to the NVM, enable a garbage collection process for the NVM, and maintain in the NVM at least said amount of dedicated unused memory. Reserving the predetermined amount of unused dedicated memory in the NVM and controlling the memory system to operate in the normal mode of operation includes reserving at least one specific unused dedicated memory portion in the NVM and controlling the memory system such that during the normal mode of operation the host's write access to the dedicated memory portion is disabled.

Abstract: Field error correction coding is particularly suitable for applications in non-volatile flash memories. We describe a method for error correction encoding of data to be stored in a memory device, a corresponding method for decoding a codeword matrix resulting from the encoding method, a coding device, and a computer program for performing the methods on the coding device, using a new construction for high-rate generalized concatenated (GC) codes. The codes, which are well suited for error correction in flash memories for high reliability data storage, are constructed from inner nested binary Bose-Chaudhuri-Hocquenghem (BCH) codes and outer codes, preferably Reed-Solomon (RS) codes. For the inner codes extended BCH codes are used, where only single parity-check codes are applied in the first level of the GC code. This enables high-rate codes.

Abstract: Field error correction coding is particularly suitable for applications in non-volatile flash memories. We describe a method for error correction encoding of data to be stored in a memory device, a corresponding method for decoding a codeword matrix resulting from the encoding method, a coding device, and a computer program for performing the methods on the coding device, using a new construction for high-rate generalized concatenated (GC) codes. The codes, which are well suited for error correction in flash memories for high reliability data storage, are constructed from inner nested binary Bose-Chaudhuri-Hocquenghem (BCH) codes and outer codes, preferably Reed-Solomon (RS) codes. For the inner codes extended BCH codes are used, where only single parity-check codes are applied in the first level of the GC code. This enables high-rate codes.

Abstract: The invention relates to a soft input decoding method and a decoder for generalized concatenated (GC) codes. The GC codes are constructed from inner nested block codes, such as binary Bose-Chaudhuri-Hocquenghem, BCH, codes and outer codes, such as Reed-Solomon, RS, codes. In order to enable soft input decoding for the inner block codes, a sequential stack decoding algorithm is used. Ordinary stack decoding of binary block codes requires the complete trellis of the code. In one aspect, the present invention applies instead a representation of the block codes based on the trellises of supercodes in order to reduce the memory requirements for the representation of the inner codes. This enables an efficient hardware implementation. In another aspect, the present invention provides a soft input decoding method and device employing a sequential stack decoding algorithm in combination with list-of-two decoding which is particularly well suited for applications that require very low residual error rates.

Abstract: Various embodiments are related to non-volatile memories, systems, and methods of using such. Some instances provide a computer readable medium that includes instructions executable by one or more processors of an NVM controller for controlling a NVM using memory pages where the NVM controller having a predefined error correction coding, ECC, capability (ECCCTRL). Executing the instructions may cause the NVM controller to: perform a monitoring process and perform a transitioning process.

Abstract: Various embodiments are related to non-volatile memories, systems, and methods of using such.

Abstract: A soft input decoding method and a decoder for generalized concatenated (GC) codes. The GC codes are constructed from inner nested block codes, such as binary Bose-Chaudhuri-Hocquenghem, BCH, codes and outer codes, such as Reed-Solomon, RS, codes. In order to enable soft input decoding for the inner block codes, a sequential stack decoding algorithm is used. Ordinary stack decoding of binary block codes requires the complete trellis of the code. In one aspect, the present invention applies instead a representation of the block codes based on the trellizes of supercodes in order to reduce the memory requirements for the representation of the inner codes. This enables an efficient hardware implementation. In another aspect, there is provided a soft input decoding method and device employing a sequential stack decoding algorithm in combination with list-of-two decoding which is particularly well suited for applications that require very low residual error rates.

Abstract: Various embodiments are related to non-volatile memories, systems, and methods of using such.

Abstract: Embodiments are generally related to the field of channel and source coding of data to be sent over a channel, such as a communication link or a data memory. Some specific embodiments are related to a method of encoding data for transmission over a channel, a corresponding decoding method, a coding device for performing one or both of these methods and a computer program comprising instructions to cause said coding device to perform one or both of said methods.

Abstract: Field error correction coding is particularly suitable for applications in non-volatile flash memories. We describe a method for error correction encoding of data to be stored in a memory device, a corresponding method for decoding a codeword matrix resulting from the encoding method, a coding device, and a computer program for performing the methods on the coding device, using a new construction for high-rate generalized concatenated (GC) codes. The codes, which are well suited for error correction in flash memories for high reliability data storage, are constructed from inner nested binary Bose-Chaudhuri-Hocquenghem (BCH) codes and outer codes, preferably Reed-Solomon (RS) codes. For the inner codes extended BCH codes are used, where only single parity-check codes are applied in the first level of the GC code. This enables high-rate codes.

Abstract: A soft input decoding method and a decoder for generalized concatenated (GC) codes. The GC codes are constructed from inner nested block codes, such as binary Bose-Chaudhuri-Hocquenghem, BCH, codes and outer codes, such as Reed-Solomon, RS, codes. In order to enable soft input decoding for the inner block codes, a sequential stack decoding algorithm is used. Ordinary stack decoding of binary block codes requires the complete trellis of the code. In one aspect, the present invention applies instead a representation of the block codes based on the trellises of supercodes in order to reduce the memory requirements for the representation of the inner codes. This enables an efficient hardware implementation. In another aspect, there is provided a soft input decoding method and device employing a sequential stack decoding algorithm in combination with list-of-two decoding which is particularly well suited for applications that require very low residual error rates.

Abstract: A method renews data in a flash memory which is organized in memory units and whose memory units which have been written to are error-protected using ECC words. The memory units which have been written to are test-read in regularly activated test-reading cycles, and either individual memory units which have been written to or all memory units which have been written to are renewed on the basis of the ECC error states which have occurred in a test-reading cycle.

Abstract: A method renews data in a flash memory which is organized in memory units and whose memory units which have been written to are error-protected using ECC words. The memory units which have been written to are test-read in regularly activated test-reading cycles, and either individual memory units which have been written to or all memory units which have been written to are renewed on the basis of the ECC error states which have occurred in a test-reading cycle.

Abstract: Data bits are programmed in cells of a flash memory which is divided into a multiplicity of separately erasable physical blocks, which are in turn split into individual physical pages to which the data bits can be written. The data bits are held in multilevel cells that store one lower bit and one upper bit per cell. The four states of which are distinguished by three voltage threshold values. The lower states are associated with the lower bit and the upper states are associated with the upper bit. The pages are distinguished by lower pages allocated to the lower bits, and upper pages allocated to the upper bits. Lower and upper pages which contain the same cells are combined by a pairing table to form paired pages. Reliable storage of data bits is achieved by programming paired pages with the same data bits and listing them as reliable paired pages in management data for the flash memory.

Abstract: An apparatus and a method for correcting data errors in a data block. The data block contains original data which are supplemented by such a security syndrome that the data block effects a correction of at most t data errors, wherein a parallel-operating quick corrector is used. The quick corrector is only designed for a correction of a subset t1 of the set of the at most t data errors, and the quick corrector includes a test encoder, which sets a first test state flag P1 which, in the event of a complete correction of a processed data block, outputs this data block and secondly activates a series-operating post-corrector for at most t data errors. The output signal of the post-corrector is output as an alternative.

Abstract: A method for addressing memory pages of a non-volatile memory in a memory system with a memory controller and a further volatile memory. The non-volatile memory is organized in erasable memory blocks with a multiplicity of memory pages, and each memory page, containing a number of sectors, can be written individually. The volatile memory holds an address translation table specifying an assignment of logical memory page addresses to physical memory page addresses. By way of the memory controller, a reconstruction table is stored as a copy of the address translation table in one or more memory blocks in the non-volatile memory, a log book table with data records containing changed assignments of logical memory page addresses to physical memory page addresses, is carried in the volatile memory and, if the log book table exceeds a predetermined size, a changed reconstruction table is stored in the non-volatile memory.