Abstract: To demodulate the RDS signal, the stereo-multiplex signal is multiplied in a first branch by the in-phase component of an oscillator, filtered by a low-pass filter while decimated in its sampling rate and filtered by a high-pass filter, while in a second branch it is multiplied by the quadrature component of the oscillator, filtered by a low-pass filter, decimated in its sampling rate, and filtered by a high-pass filter. An error signal to control the oscillator is calculated from the high-pass-filtered signals and the RDS bit clock. A clock generator generating the RDS bit clock is controlled by the first high-pass-filtered signal and by the oscillator. An RDS decoder, to whose input the first high-pass-filtered signal is applied, and an arithmetic unit which calculates the error signal from the high-pass-filtered signals and from the RDS bit clock are both clocked by the clock generator. The RDS data are retrievable from the output of the RDS decoder.

Abstract: To demodulate the RDS signal, the stereo-multiplex signal is multiplied in a first branch by the in-phase component of an oscillator filtered by a low-pass filter while decimated in its sampling rate and filtered by a high-pass filter while in a second branch it is multiplied by the quadrature component of the oscillator filtered by a low-pass filter decimated in its sampling rate, and filtered by a high-pass filter. An error signal to control the oscillator is calculated from the high-pass-filtered signals and the RDS bit clock. A clock generator generating the RDS bit clock is controlled by the first high-pass-filtered signal and by the oscillator. An RDS decoder, to whose input the first high-pass-filtered signal is applied. and an arithmetic unit which calculates the error signal from the high-pass-filtered signals and from the PDS bit clock are both clocked by the clock generator. The RDS data are retrievable from the output of the RDS decoder.

Abstract: For the purpose of largely suppressing the noise pulses caused in a stereo radio receiver in the reception signal, particularly by the ignition system of a motor vehicle, a digital field strength signal representing the analog field strength signal is produced for example by digitizing the analog field strength signal. The scanning values of the digital audio signal, for example of the (L+R) signal, are produced by interpolation for at least as long as the digital field strength signal is outside a presettable tolerance range.

Abstract: A radio signal receiver is tunable to a plurality of different reception frequencies and is set up to output a signal obtained from a radio signal received at a tuned frequency to a reproducer in an operating mode (S8), and to acquire information at least about the identity of a transmitter receivable at a given frequency in a standby mode (S2-S7), and to record said information in a memory. The receiver is set up, initially when switched on, to acquire and record (S3) information on a plurality of transmitters in a standby mode (S2-S7), before switching over to the operating mode (S8). The receiver may be operated together with a control unit which is coupled to at least one sensor and is set up to turn the receiver on and/or off depending on the detection result of the at least one sensor.

Abstract: To generate the RDS bit clock in a car radio, a comparison is made between the period of a clock generator and the period of the demodulated RDS signal. A first counter that triggers the clock generator, counts the zero crossings in the RDS carrier detected by a first zero crossing detector. A second counter counts sampled values of the demodulated RDS signal lying between two zero crossings detected by a second zero crossing detector. If the number of sampled values counted by the second counter lies within a presettable tolerance range, an arithmetic unit calculates a synchronizing signal to synchronize the clock generator with the RDS data stream. The synchronizing signal increments or decrements the count of the first counter to achieve synchronization between the clock generator and the RDS data stream.

Abstract: The sound reproduction of a multichannel sound reproduction system with a plurality of speakers which is connected to the output of an FM stereo receiver is controlled by a control signal derived from the reception quality. Preferably, the control signal from the FM stereo receiver for controlling the stereo and mono components is also employed to control the multichannel sound reproduction system. For example, stereo, pseudo-stereo or mono reproduction are provided in the multichannel sound reproduction system in response to the stereo component within the output signal.

Abstract: To ensure that a phase-locked loop locks quickly to the pilot tone of the stereo-multiplex signal when a new transmitter is tuned in, the stereo-multiplex signal is multiplied in a multiplier M by the quadrature component of the pilot tone generated by a digital oscillator, is low-pass-filtered in a low-pass filter, and is fed as a control signal to the oscillator which is composed of a table of length N and a counter for addressing the table entries. The zero phase angle &phgr;0 is set by a counter offset n0 by incrementing or decrementing the counter. It is advantageous to employ a virtual table of length N+ which is larger than the length N of the real table. To access the real table, however, only the corresponding MSBs of the actual count n(k) are used which match the address space of the real table of length N.

Abstract: To demodulate the RDS signal, the stereo-multiplex signal is multiplied in a first branch by the in-phase component of an oscillator, filtered by a low-pass filter while decimated in its sampling rate and filtered by a high-pass filter, while in a second branch it is multiplied by the quadrature component of the oscillator, filtered by a low-pass filter, decimated in its sampling rate, and filtered by a high-pass filter. An error signal to control the oscillator is calculated from the high-pass-filtered signals and the RDS bit clock. A clock generator generating the RDS bit clock is controlled by the first high-pass-filtered signal and by the oscillator. An RDS decoder, to whose input the first high-pass-filtered signal is applied, and an arithmetic unit which calculates the error signal from the high-pass-filtered signals and from the RDS bit clock are both clocked by the clock generator. The RDS data are retrievable from the output of the RDS decoder.