Abstract: This invention relates to a method for operating a variable impedance load on a device consisting of a planar transformer, consisting of at least a primary and a secondary side, which can be operated as input or output side, comprising primary and secondary coils, wherein capacitances between windings of a coil form a resonant circuit with inductances of the coil. This coil comprises a selection of a resonance frequency of the resonant circuit, wherein the resonance frequency falls on a frequency of a harmonic of an input signal to be suppressed.

Abstract: The invention relates to a method for operating a variable impedance load on a device, consisting of a planar transformer, consisting of at least a primary and a secondary side, which can be operated as an input or output side, comprising mapping an image of a virtual RF ground at the point of symmetry of one of the secondary sides to a first impedance.

Abstract: An electronic circuit and method for designing an electronic circuit is provided that includes a first source element, a second source element, a first matching network, and a second matching network. The first matching network and the second matching network are designed by means of a method using the Poincaré distance, in which the second source element is designed to output a signal with a center frequency, in which the load has a load impedance, in which the second matching network has line-like series elements that carry the signal. The line-like series elements only have line impedances less than the load impedance or a sum of the electrical lengths of the line-like series elements, each of which has a line impedance greater than the load impedance, is less than one quarter of a wavelength associated with the signal.

Abstract: An electronic circuit and method for designing an electronic circuit is provided that includes a first source element, a second source element, a first matching network, and a second matching network. The first matching network and the second matching network are designed by means of a method using the Poincaré distance, in which the second source element is designed to output a signal with a center frequency, in which the load has a load impedance, in which the second matching network has line-like series elements that carry the signal. The line-like series elements only have line impedances less than the load impedance or a sum of the electrical lengths of the line-like series elements, each of which has a line impedance greater than the load impedance, is less than one quarter of a wavelength associated with the signal.

Abstract: A method for designing a circuit, particularly having an active component, preferably a high-frequency circuit, wherein: (a) a plurality of load lines is determined at least approximately; (b) a course of a small-signal parameter along each load line is determined at least approximately; (c) a region of each load line is determined as a load line subset, distinguished by a characteristic property dependent on the small-signal parameter; and (d) a large-signal parameter, assigned to the load line, is determined at least approximately from the course of the small-signal parameter within the region.

Abstract: A method for the integration of two bipolar transistors in a semiconductor body, wherein, for the first bipolar transistor, a first emitter semiconductor region, a first base semiconductor region, and a first collector semiconductor region are produced. A recombination layer is applied to the first bipolar transistor, which is adjacent to the first emitter semiconductor region or the first collector semiconductor region and is constructed in such a way that charge carriers recombine on the recombination layer, and next, the second bipolar transistor is placed on the recombination layer, wherein a second emitter semiconductor region, a second base semiconductor region, and a second collector semiconductor region are produced on the recombination layer, so that the second emitter semiconductor region or the second collector semiconductor region is adjacent to the recombination layer.

Abstract: A high frequency arrangement is provided that includes an integrated high frequency circuit, a first bond pad, which is electrically connected by a first electrical supply line, in particular a bond wire and/or a solder bump, to a housing terminal and/or another circuit, wherein the first bond pad adjoins a dielectric so that the first bond pad forms a first capacitance with the dielectric and an electrically conductive region of the integrated high-frequency circuit, and the first capacitance and the first supply line, which has an inductance, influence a (tuned) first resonant frequency associated with the high-frequency circuit.

Abstract: A method for manufacturing a semiconductor array, particularly a high-frequency bipolar transistor, is provided, the method includes process steps, so that a dielectric is produced on a mono-crystalline, first semiconductor region of a first conductivity type, a silicide layer is deposited and patterned in such a way that the silicide layer is insulated from the first semiconductor region by the dielectric, and, to form a base region, a second semiconductor region of a second conductivity type is applied to the first semiconductor region and to the silicide layer in such a way that the second semiconductor region lies with a first interface on the first semiconductor region and with a second interface on the silicide layer.

Abstract: A process for producing a base connection of a bipolar transistor is provided. The process includes the steps of providing a semiconductor structure that can include a three-dimensional sacrificial structure that is selectively removable with respect to adjacent regions. A first semiconductor layer and a second layer of dielectric material is deposited. The first semiconductor layer is partially exposed by partial removal of the second layer. A first reaction layer is deposited that, together with the first semiconductor layer forms reaction products, which are selectively removable with respect to adjacent regions. Remaining material of the first reaction layer that has not reacted with the material of the first semiconductor layer is removed. A second reaction layer is deposited that, with the first semiconductor layer, forms a low-resistivity compound. Remaining material of the second reaction layer that has not reacted with the material of the first semiconductor layer is removed.

Abstract: An integrated circuit layout having a first circuit connection, a second circuit connection, and active components is provided, whereby the active components each have an input connection and an output connection and a predefined maximum reverse voltage between the input connection and the output connection, and whereby a maximum value of a voltage swing, achieved between the first circuit connection and the second circuit connection, is greater than the predefined maximum reverse voltage. The circuit layout is characterized in that an input connection of an n-th active component is connected to an output connection of an (n?1)-th active component, and that the circuit layout changes the potentials of terminal gates of the (n?1)-th component and the n-th component synchronously to a control signal.

Abstract: A method for manufacturing a semiconductor article and a semiconductor article is provided, wherein a base region of a first semiconductor material is applied, a silicide layer is applied above the base region, after the application of the silicide layer, an opening is created in the silicide layer by removing the silicide layer within the area of the opening, and after this, an emitter region is formed within the opening.

Abstract: Amplifier circuit for amplifying an input signal, having a vertically integrated cascode that has a collector semiconductor region of a collector, adjacent to the collector semiconductor region, a first base semiconductor region of a first base, a second base semiconductor region of a second base, an intermediate base semiconductor region adjoining both the first base semiconductor region and the second base semiconductor region, and an emitter semiconductor region of an emitter adjacent to the second base semiconductor region, wherein a signal input is connected to the second base, and the first base is electrically coupled both to a voltage source that is independent of the input signal and to the collector.

Abstract: A differential cascode amplifier is disclosed that includes in each branch two transistors connected to form a cascode circuit, and has a cross-compensation (neutralization) with at least one pair of capacitors for compensating a parasitic capacitance of a transistor of each branch, wherein in each case, one capacitor of the pair is equal to the parasitic capacitance of the transistor of the associated branch.

Abstract: A method for integrating three bipolar transistors into a semiconductor body, multilayer component, and semiconductor arrangement is provided. A tendency toward thyristor-like behavior of the multilayer semiconductor arrangements with the three bipolar transistors is suppressed with the aid of a heterojunction. The high frequency characteristics and the blocking capability of the circuit of the three bipolar transistors is made more flexible, while the capability of an input signal to control an output signal is maintained.

Abstract: A process for manufacturing a semiconductor device, provides that a silicide layer is formed, an amorphous semiconductor layer is applied both to the silicide layer and to an open monocrystalline semiconductor region, adjacent to the silicide layer, and during a subsequent temperature treatment, the amorphous semiconductor layer is crystallized proceeding from the open, monocrystalline semiconductor region, acting as a crystallization nucleus, so that the silicide layer is covered at least partially by a crystallized, monocrystalline semiconductor layer.

Abstract: Amplifier circuit for amplifying an input signal, having a vertically integrated cascode that has a collector semiconductor region of a collector, adjacent to the collector semiconductor region, a first base semiconductor region of a first base, a second base semiconductor region of a second base, an intermediate base semiconductor region adjoining both the first base semiconductor region and the second base semiconductor region, and an emitter semiconductor region of an emitter adjacent to the second base semiconductor region, wherein a signal input is connected to the second base, and the first base is electrically coupled both to a voltage source that is independent of the input signal and to the collector.

Abstract: A method for structuring a laterally extending first layer in a semiconductor device with the aid of a reactive second layer, which together with the first layer to be structured forms first reaction products, which products are removed by material removal that acts selectively on the first reaction products, whereby the structuring takes place in a vertical direction.

Abstract: A cascode of a high-frequency circuit, includes a first transistor having a first base semiconductor region, a first collector semiconductor region and a first emitter semiconductor region, and a second transistor having a second base semiconductor region, a second collector semiconductor region and a second emitter semiconductor region. The first emitter semiconductor region of the first transistor and the second collector semiconductor region of the second transistor are geometrically arranged on top with respect to a wafer surface, while the first collector semiconductor region of the first transistor and the second emitter semiconductor region of the second transistor are geometrically arranged on the bottom with respect to the wafer surface.

Abstract: A process for manufacturing a semiconductor device, provides that a silicide layer is formed, an amorphous semiconductor layer is applied both to the silicide layer and to an open monocrystalline semiconductor region, adjacent to the silicide layer, and during a subsequent temperature treatment, the amorphous semiconductor layer is crystallized proceeding from the open, monocrystalline semiconductor region, acting as a crystallization nucleus, so that the silicide layer is covered at least partially by a crystallized, monocrystalline semiconductor layer.

Abstract: An amplifier circuit is provided for amplifying an input signal with a vertically integrated cascode. The cascode comprises a collector semiconductor region of a collector, a first base semiconductor region, adjacent to the collector semiconductor region, of a first base, a second base semiconductor region of a second base, an intermediate base semiconductor region adjacent to both the first base semiconductor region and the second base semiconductor region, and an emitter semiconductor region, adjacent to the second base semiconductor region, of an emitter. A signal input is connected to the second base and the first base is connected via a network to the second base in such a way that a small signal voltage at the first base is coupled to a small signal voltage at the second base and/or a small signal current through the second base.