Abstract: Output data points of a digital FIR filter are calculated by storing input data points in an addressable memory and accessing the addressable memory to supply a new input data point exactly once for each output data point after a first output data point and storing each input data point in a first recirculating memory for so long as that input data point is needed to calculate a next output data point. The input data points stored in the first recirculating memory are used to calculate output data points. Furthermore, coefficients are stored in a second recirculating memory and are used to calculate the output data points. As a result, only one memory access is required per output data point.

Abstract: A sequentially accessible, non-volatile data storage circuit for generating constants includes a logic array for non-volatile storage of programmed data words and a recirculating shift register for causing the first one of the data words to appear at a data output of the data storage circuit in response to a reset signal and to cause the next data word to appear at the data output in response to a clock signal.

Abstract: According to a technique for determining delays through multi-stage datapath elements, estimates of the delays through each stage of the datapath element are computed in accordance with an the equation such as:D.sub.s =D.sub.b N.sub.b +Cwhere D.sub.s is the estimated stage delay, D.sub.b is a delay associated with communication between bits in the stage, N.sub.b is the number of bits in the datapath element, and C is a constant. The estimated stage delays are used to determine positions of pipelining stages in the datapath element.

Abstract: According to a method for designating the locations of pipelining stages in multi-stage datapath elements, the delay associated with each stage of the multi-stage element is estimated. Then, beginning with a designated stage of the multi-stage element, the estimated delays for the individual stages are added to obtain an accumulated delay time. Whenever the accumulated delay time exceeds a desired cycle time, a pipelining stage is inserted into the multi-stage element prior to the stage which caused the accumulated delay time to exceed the desired operating cycle time. Then, the method is continued for succeeding stages in the datapath element until all of its stages have been accounted for.

Abstract: A conditional-sum carry structure has an architecture which is sufficiently regular that the structure can be conveniently generated by an automated compiler. The carry structure includes a column of input cells, each of the cells in the column being operative for receiving binary numbers and, for each of the received numbers, generating a sum bit and two carry-out bits. Further the carry structure includes an array of columns of binary logic elements comprised of dual multiplexers (MUX MUX elements), dual exclusive OR gates (XOR XOR elements), multiplexer and exclusive OR gate circuits (MUX XOR elements) and multiplexer units (ONE MUX elements) for receiving sum bits and carry-out bits from the input cells and for performing the operations of a conditional-sum carry structure.