Abstract: A device tests the function of an antenna system. The antenna system has a plurality of antennas that are interconnected with an assigned input of a selection unit. The antennas of a first antenna group are interconnected with the inputs of a first multiplexer. The antennas of a second antenna group are interconnected with the inputs of a second multiplexer. The antennas of the first and second antenna groups are arranged adjacently and/or overlap in pairs. A computing unit provides control signals for the selection unit to feed an AC signal into a selected antenna of the first antenna group and to capture the antenna signal present on each antenna of the second antenna group for the selected antenna at an output of the selection unit. A fault is inferred from the comparison of the determined antenna signals for the selected antenna and associated expected antenna signals.

Abstract: A device tests the function of an antenna system which includes antenna units each having an antenna and a resistor and is connected between an input of a selection unit and an output of a further selection unit. A computing unit provides a control signal for the two selection units at a first output. The control signal determines which input is connected to an output of the selection unit, and which of the outputs of a further selection unit is supplied with a bias voltage present at the input of the further selection unit, and to receive the antenna signal present at the output of the selection unit at an input of the computing unit. A diagnosis circuit is connected between the output of the selection unit and a diagnosis voltage terminal. The computing unit infers a fault in the antenna system from the comparison of antenna signals.

Abstract: A device tests the function of an antenna system. The antenna system has a plurality of antennas that are interconnected with an assigned input of a selection unit. The antennas of a first antenna group are interconnected with the inputs of a first multiplexer. The antennas of a second antenna group are interconnected with the inputs of a second multiplexer. The antennas of the first and second antenna groups are arranged adjacently and/or overlap in pairs. A computing unit provides control signals for the selection unit to feed an AC signal into a selected antenna of the first antenna group and to capture the antenna signal present on each antenna of the second antenna group for the selected antenna at an output of the selection unit. A fault is inferred from the comparison of the determined antenna signals for the selected antenna and associated expected antenna signals.

Abstract: A device tests the function of an antenna system which includes antenna units each having an antenna and a resistor and is connected between an input of a selection unit and an output of a further selection unit. A computing unit provides a control signal for the two selection units at a first output. The control signal determines which input is connected to an output of the selection unit, and which of the outputs of a further selection unit is supplied with a bias voltage present at the input of the further selection unit, and to receive the antenna signal present at the output of the selection unit at an input of the computing unit. A diagnosis circuit is connected between the output of the selection unit and a diagnosis voltage terminal. The computing unit infers a fault in the antenna system from the comparison of antenna signals.

Abstract: An integrated circuit includes a reception port an address port, and a memory with a number of memory sections for storing activation information. The number of memory sections is equal to the number, encodable by the address port, of activatable integrated circuits that are operable over a common bus. A control unit is configured to compare the address encoded by the address port with an address received at the reception port. The control unit writes a defined bit pattern to the memory section associated with the address in the event of a positive comparison, and withholds transmission of a negative acknowledgement signal in the event of a negative comparison. The integrated circuit is configured to be activated by the defined bit pattern in the memory section that corresponds to the address defined at the address port, for communicating with a microprocessor connected to the integrated circuit via the common bus.

Abstract: A method for operating a circuit for charging and discharging a capacitive actuator. The circuit has a series circuit of first and second power transistors with respective parallel-connected diodes connected between the potentials of a supply voltage source. The node between the power transistors is connected via a coil to the capacitive actuator. For charging the actuator, the first power transistor, which connects the capacitive actuator to the positive potential, is periodically turned on during a prescribed time and turned off when a first prescribed threshold value is reached by the current through the actuator, until a lower threshold value is reached by the current. If the actuator current no longer reaches the first prescribed threshold value then the first power transistor is turned off after a time that corresponds to the maximum value reached by the actuator current.

Abstract: An integrated circuit includes a reception port an address port, and a memory with a number of memory sections for storing activation information. The number of memory sections is equal to the number, encodable by the address port, of activatable integrated circuits that are operable over a common bus. A control unit is configured to compare the address encoded by the address port with an address received at the reception port. The control unit writes a defined bit pattern to the memory section associated with the address in the event of a positive comparison, and withholds transmission of a negative acknowledgement signal in the event of a negative comparison. The integrated circuit is configured to be activated by the defined bit pattern in the memory section that corresponds to the address defined at the address port, for communicating with a microprocessor connected to the integrated circuit via the common bus.

Abstract: A switching controller for the generation of a plurality of DC voltages includes an auxiliary secondary circuit in addition to a primary circuit and at least two main secondary circuits. Only the auxiliary secondary circuit is controlled by a control circuit. The auxiliary secondary circuit operates in a virtually powerless manner, wherein the time constant of a parallel circuit has a third output capacitor and an auxiliary load resistor is smaller than the average time constants of at least the first and second main secondary circuits, which are defined by the output capacitors thereof and the average rating values of the load resistors to be connected.

Abstract: A switching controller for the generation of a plurality of DC voltages includes an auxiliary secondary circuit in addition to a primary circuit and at least two main secondary circuits. Only the auxiliary secondary circuit is controlled by a control circuit. The auxiliary secondary circuit operates in a virtually powerless manner, wherein the time constant of a parallel circuit has a third output capacitor and an auxiliary load resistor is smaller than the average time constants of at least the first and second main secondary circuits, which are defined by the output capacitors thereof and the average rating values of the load resistors to be connected.

Abstract: A method for operating a circuit for charging and discharging a capacitive actuator. The circuit has a series circuit of first and second power transistors with respective parallel-connected diodes connected between the potentials of a supply voltage source. The node between the power transistors is connected via a coil to the capacitive actuator. For charging the actuator, the first power transistor, which connects the capacitive actuator to the positive potential, is periodically turned on during a prescribed time and turned off when a first prescribed threshold value is reached by the current through the actuator, until a lower threshold value is reached by the current. If the actuator current no longer reaches the first prescribed threshold value then the first power transistor is turned off after a time that corresponds to the maximum value reached by the actuator current.

Abstract: An apparatus and a method for recognizing an error in a power bridge circuit containing a load, a high-side branch and a low-side branch. Accordingly, a first switched current source is connected to the load and to a diagnosis connection for a high-potential of a diagnosis voltage, a second switched current source is connected to the load and to a diagnosis connection for a low-potential of the diagnosis voltage, and a control device for controlling the first switched current source and the second switched current source. The control device switches on one of the switched current sources when the high-side power switch and the low-side power switch are open, while the other switched current source is switched off. A testing device tests a voltage at the load when one of the switched current sources is switched on and the other of the switched current sources is switched off.

Abstract: A circuit for controlling an inductive load, e.g. of a fuel injection valve, includes supply terminals for supplying a voltage, output terminals for connecting the load, and a detection device which is connected to at least one of the output terminals and is used for detecting the point in time at which the operation of the load is discontinued and/or detecting at least one fault case during a non-operational phase of the load. In order to render the detection process more reliable while using less circuitry, the detection device encompasses a current mirror with a first current source and a second current source. The current first is connected to one of the two output terminals during a detection phase. The current supplied by the second current source is evaluated as a signal of the detected result.

Abstract: An apparatus and a method for recognizing an error in a power bridge circuit containing a load, a high-side branch and a low-side branch. Accordingly, a first switched current source is connected to the load and to a diagnosis connection for a high-potential of a diagnosis voltage, a second switched current source is connected to the load and to a diagnosis connection for a low-potential of the diagnosis voltage, and a control device for controlling the first switched current source and the second switched current source. The control device is configured so that it switches on one of the switched current sources when the high-side power switch and the low-side power switch are open, while the other switched current source is switched off. A testing device is provided to test a voltage at the load when one of the switched current sources is switched on and the other of the switched current sources is switched off.

Abstract: A circuit for controlling an inductive load, e.g. of a fuel injection valve, includes supply terminals for supplying a voltage, output terminals for connecting the load, and a detection device which is connected to at least one of the output terminals and is used for detecting the point in time at which the operation of the load is discontinued and/or detecting at least one fault case during a non-operational phase of the load. In order to render the detection process more reliable while using less circuitry, the detection device encompasses a current mirror with a first current source and a second current source. The current first is connected to one of the two output terminals during a detection phase. The current supplied by the second current source is evaluated as a signal of the detected result.

Abstract: A method for actuating a solenoid valve generates precise opening and closing times of the solenoid valve. To this end, an actuating current provided for actuating the solenoid valve and applied to an actuating coil of the solenoid valve is already reducing in a reduction phase prior to a switch-off point in time of the solenoid valve relative to a maintained level of the actuating current, at which the solenoid valve is reliably held in an actuating position.