Abstract: A preprocessing technique for synthetic radar images. An embodiment of a method for preprocessing synthetic aperture radar images includes: receiving range-compressed radar data generated from raw radar image data on-board a satellite or an airborne vehicle; generating a preliminary SAR image by performing a pre-focusing on the range-compressed radar data; extracting image subsectors from the preliminary SAR image; transmitting the extracted image subsectors to an on-ground portion; reconstructing the range-compressed radar data pertaining to the extracted image subsectors; and making the range-compressed radar data pertaining to the extracted image subsectors available for a Nominal synthetic aperture radar processor, wherein the Nominal synthetic aperture radar processor is configured to generate a focused SAR image having a nominal value of image resolution that is higher than the resolution of the preliminary SAR image.

Abstract: A preprocessing technique for synthetic radar images. An embodiment of a method for preprocessing synthetic aperture radar images includes: receiving range-compressed radar data generated from raw radar image data on-board a satellite or an airborne vehicle; generating a preliminary SAR image by performing a pre-focusing on the range-compressed radar data; extracting image subsectors from the preliminary SAR image; transmitting the extracted image subsectors to an on-ground portion; reconstructing the range-compressed radar data pertaining to the extracted image subsectors; and making the range-compressed radar data pertaining to the extracted image subsectors available for a Nominal synthetic aperture radar processor, wherein the Nominal synthetic aperture radar processor is configured to generate a focused SAR image having a nominal value of image resolution that is higher than the resolution of the preliminary SAR image.

Abstract: A logic circuit includes at least one register and a corresponding comparator coupled to the register and an input data node. A multiplexer is coupled to the register. A control block is coupled to the multiplexer, the comparator, the input node and an input control node.

Abstract: The invention relates to a circuit arrangement for data stream distribution with conflict resolution, whereby data streams are transmitted bi-directionally, such that first data stream connection units (104a-104n) and second data stream connection units (105a-105m) serve as both input and output connections. A distribution unit (100), essentially comprises a matrix switching unit (101), first intermediate buffer units (106a-106n) and second intermediate buffer units (107a-107m). Information is firstly evaluated in the cell head, which, together with information on the availability of intermediate buffer units, determine when a present data stream cell may be transmitted to a relevant output connection unit.

Abstract: The invention relates to a circuit arrangement for data stream distribution with conflict resolution, whereby data streams are transmitted bi-directionally, such that first data stream connection units (104a-104n) and second data stream connection units (105a-105m) serve as both input and output connections. A distribution unit (100), essentially comprises a matrix switching unit (101), first intermediate buffer units (106a-106n) and second intermediate buffer units (107a-107m). Information is firstly evaluated in the cell head, which, together with information on the availability of intermediate buffer units, determine when a present data stream cell may be transmitted to a relevant output connection unit.

Abstract: A logic circuit realizes an “if then else” branch based upon information carried at an input node and information stored in a register. The logic circuit includes at least one register and a corresponding comparator coupled to the register and an input data node. A multiplexer is coupled to the register. A control block is coupled to the multiplexer, the comparator, the input node and an input control node.