Abstract: An optical output device is described that includes one bus system. The bus system includes two bus wires of a bus, two bus units and one bus control unit. The two bus units may include one optical output element one output control unit whose output is connected to the one optical output element a first storage unit for storing address data of the respective bus unit a second storage unit for storing a counter value, a comparison unit whose inputs are connected to the first storage unit and to the second storage unit, and a control unit whose input is connected to an output of the comparison unit and which controls the takeover of data from the bus into the output control unit depending on an output signal or on output data of the comparison unit.

Abstract: Described is an adapter (1120) for a device, especially for a USB device (1130).

Abstract: Disclosed is an input device (I, 710), preferably a computer mouse (710), comprising: —a memory unit (M) for storing at least one parameter value (D1 to D6), wherein the at least one parameter value (D1 to D6) defines how an electrical signal (310) that is generated during a user input operation has to be processed within the input device (1, 710), a change signal generation unit comprising at least one of:—a receiving unit (720) that is configured to receive a modification value from outside of the input device (I, 710), —at least one input element (717) that is configured to receive a modification value input by a user, wherein the modification value input is processed directly within the input device (I, 710), —or a modification value generating unit that is configured to generate a modification value within the input device (I, 710), wherein the change signal generation unit is configured to generate a change signal depending on the modification value, and —a control unit (718) that is configured to chang

Abstract: A method for implicit addressing includes providing within a first unit and a second unit respectively a counter unit, a comparison unit and a storing unit for the storage of an identifier, allocating a first identifier to the first unit, allocating a second identifier to the second unit setting the same counter value in the counter units of both units, after setting the counter values comparing the counter value in the first unit to the first identifier and comparing the counter value in the second unit to the second identifier, based on equality of the comparison in the first unit sending of first data from the first unit or-assigning of first data to the first unit, based on inequality of the comparison in the second unit no sending or assigning of data to the second unit, and counting up or down the counter value in both units.

Abstract: A device, preferably USB device, including at least one memory unit which is configured to store a firmware program including instructions and at least one interface unit which is configured to forward data to a main processing device according to the USB specification. At least one processor which is configured to perform the instructions of the firmware program, wherein the processor is configured to be externally triggered by trigger events to send at least one data packet including the data to be forwarded via the interface unit.

Abstract: A method includes providing a first and second electronic unit unit, generating a wirelessly transmitted signal for detecting or generating one signal or several signals for detection on a chain of electronic elements, for the first unit, detecting a transmission time of the wirelessly transmitted signal for detection or detecting a first transmission time on a first of the chain, for the second unit, detecting a second value or the transmission time of the wirelessly transmitted signal for detection or detecting a second value or a second transmission time on a second position of the chain that is different from the first position, converting the first value or the transmission time detected for the first unit to a first address for the first unit, and converting the second value or the transmission time detected within or for the second unit to a second address for the second unit.

Abstract: The present invention refers to a method for operating an active input element and a corresponding input element, input arrangement and computer program product, comprising the steps: a) set value C of clock counter to 0 (S2); b) increase value C of clock counter by 1 and shift data in shift register (5) by one Bit, when detecting a clock information (S3); c) compare (S4) value C of clock counter with a cycle length CLL, and return to step b) if comparison result is negative or proceed to step d) if comparison result is positive; d) read data (DFIFO) from shift register (S5); e) compare (S6) said read data (DFIFO) from shift register (5) with predetermined first data value (D1), and proceed to step f) if comparison result is positive or proceed to step a) if comparison result is negative; f) write data (DIE) derived from analog input device (S) into shift register (S7) and return to step a).

Abstract: An input arrangement, especially a keyboard, including: at least two bus wires of a bus, at least 10 or at least 100 bus units which are electrically connected to the bus wires and which respectively are electrically connected to at least one input element, wherein the bus units are electrically connected in parallel connection to the bus wires.

Abstract: An optical output device is described that includes one bus system. The bus system includes two bus wires of a bus, two bus units and one bus control unit. The two bus units may include one optical output element one output control unit whose output is connected to the one optical output element a first storage unit for storing address data of the respective bus unit a second storage unit for storing a counter value, a comparison unit whose inputs are connected to the first storage unit and to the second storage unit, and a control unit whose input is connected to an output of the comparison unit and which controls the takeover of data from the bus into the output control unit depending on an output signal or on output data of the comparison unit.

Abstract: A method for implicit addressing includes providing within a first unit and a second unit respectively a counter unit, a comparison unit and a storing unit for the storage of an identifier, allocating a first identifier to the first unit, allocating a second identifier to the second unit setting the same counter value in the counter units of both units, after setting the counter values comparing the counter value in the first unit to the first identifier and comparing the counter value in the second unit to the second identifier, based on equality of the comparison in the first unit sending of first data from the first unit or-assigning of first data to the first unit, based on inequality of the comparison in the second unit no sending or assigning of data to the second unit, and counting up or down the counter value in both units.

Abstract: A method includes providing a first and second electronic unit unit, generating a wirelessly transmitted signal for detecting or generating one signal or several signals for detection on a chain of electronic elements, for the first unit, detecting a transmission time of the wirelessly transmitted signal for detection or detecting a first transmission time on a first of the chain, for the second unit, detecting a second value or the transmission time of the wirelessly transmitted signal for detection or detecting a second value or a second transmission time on a second position of the chain that is different from the first position, converting the first value or the transmission time detected for the first unit to a first address for the first unit, and converting the second value or the transmission time detected for the second unit to a second address for the second unit.

Abstract: The present invention refers to a method for operating an active input element and a corresponding input element, input arrangement and computer program product, comprising the steps: a) set value C of clock counter to 0 (S2); b) increase value C of clock counter by 1 and shift data in shift register (5) by one Bit, when detecting a clock information (S3); c) compare (S4) value C of clock counter with a cycle length CLL, and return to step b) if comparison result is negative or proceed to step d) if comparison result is positive; d) read data (DFIFO) from shift register (S5); e) compare (S6) said read data (DFIFO) from shift register (5) with predetermined first data value (Dl), and proceed to step f) if comparison result is positive or proceed to step a) if comparison result is negative; f) write data (DIE) derived from analog input device (S) into shift register (S7) and return to step a).

Abstract: The invention relates in an aspect A to a method for determining active input elements (S1a, S2a) of an input arrangement (10), comprising providing input elements (S1a to S2b) that are connected according to a matrix arrangement, providing within the matrix arrangement at least two drive lines (L1, L2) that are each connected to a respective driving circuit (2, 4), providing within the matrix arrangement at least two sense lines (Ca, Cb) that may be used to detect active input elements (S1a, S2a), providing within the matrix arrangement serial connections (SC1 to SC4) each comprising one of the input elements (S1a) and a resistor (R1a) and each serial connection (SC1 to SC4) being connected to a respective one of the drive lines (L1, L2) and to a respective one of the sense lines (Ca, Cb), providing pull resistors (Ra, Rb) that connect the sense lines (Ca, Cb) to a first potential, and using a control device for the driving circuits that drives an active drive line (L1) to a second potential that is diffe

Abstract: The invention relates in an aspect A to a method for determining active input elements (S1a, S2a) of an input arrangement (10), comprising providing input elements (S1a to S2b) that are connected according to a matrix arrangement, providing within the matrix arrangement at least two drive lines (L1, L2) that are each connected to a respective driving circuit (2, 4), providing within the matrix arrangement at least two sense lines (Ca, Cb) that may be used to detect active input elements (S1a, S2a), providing within the matrix arrangement serial connections (SC1 to SC4) each comprising one of the input elements (S1a) and a resistor (R1a) and each serial connection (SC1 to SC4) being connected to a respective one of the drive lines (L1, L2) and to a respective one of the sense lines (Ca, Cb), providing pull resistors (Ra, Rb) that connect the sense lines (Ca, Cb) to a first potential, and using a control device for the driving circuits that drives an active drive line (L1) to a second potential that is diffe