Abstract: A system and method to trigger synchronization and validation actions at memory access, in one aspect, identifies a storage class associated with a region of shared memory being accessed by a thread, determines whether the thread holds the storage class and acquires the storage class if the thread does not hold the storage class, identifies a programmable action associated with the storage class and the thread, and triggers the programmable action. One or more storage classes are respectively associated with one or more regions of shared memory. An array of storage classes associated with a thread holds one or more storage classes acquired by the thread. A configurable action table associated with a thread indicates one or more programmable actions associated with a storage class.

Abstract: A method and a system for implementing concurrent producer-consumer buffers are provided. The method and system in one aspect uses separate locks, one for putter and another for taker threads operating on a concurrent producer-consumer buffer. The locks operate independently of a notify-wait process.

Abstract: A system and method for partitioning a data stream into tokens includes steps or acts of: receiving the data stream; setting a partition scanner to a beginning point in the data stream; identifying likely token boundaries in the data stream using the partition scanner; partitioning the data stream according to the likely token boundaries as determined by the partition scanner, wherein each partition of the partitioned data stream bounded by the likely token boundaries comprises a chunk; and passing the chunk to a next available token scanner, one chunk per token scanner, for identifying at least one actual token within each chunk.

Abstract: A system for conditional memory ordering implemented in a multiprocessor environment. A conditional memory ordering instruction executes locally using a release vector containing release numbers for each processor in the system. The instruction first determines whether a processor identifier of the release number is associated with the current processor. Where it is not, a conditional registered is examined and appropriate remote synchronization operations are commanded where necessary.

Abstract: A method for executing an atomic transaction includes receiving the atomic transaction at a processor for execution, determining a transactional memory location needed in memory for the atomic transaction, reserving the transactional memory location while all computation and store operations of the atomic transaction are deferred, and performing the computation and store operations, wherein the atomic transaction cannot be aborted after the reservation, and further wherein the store operation is directly committed to the memory without being buffered.

Abstract: A system and method for partitioning a data stream into tokens includes steps or acts of: receiving the data stream; setting a partition scanner to a beginning point in the data stream; identifying likely token boundaries in the data stream using the partition scanner; partitioning the data stream according to the likely token boundaries as determined by the partition scanner, wherein each partition of the partitioned data stream bounded by the likely token boundaries comprises a chunk; and passing the chunk to a next available token scanner, one chunk per token scanner, for identifying at least one actual token within each chunk.

Abstract: A system for conditional memory ordering implemented in a multiprocessor environment. A conditional memory ordering instruction executes locally using a release vector containing release numbers for each processor in the system. The instruction first determines whether a processor identifier of the release number is associated with the current processor. Where it is not, a conditional registered is examined and appropriate remote synchronization operations are commanded where necessary.

Abstract: A computer-implemented method for managing concurrent transactions includes recording locations written by a first transaction in a first Bloom filter, recording locations to be read by a second transaction in a second Bloom filter, and performing one of a cancellation or a commission of the second transaction based on an intersection of the first Bloom filter and the second Bloom filter.

Abstract: A system, method and computer program product for processing overflow transactions in a transactional memory system. The transactional memory system is provided in a multiprocessing system having one or more processor devices and a shared memory storage system, and implements a best effort hardware transactional memory system. The method includes acquiring, by a requesting processor, lockbits associated with a memory structure of the shared memory storage system to be reserved for an overflowing transaction. The lockbits determine the granularity at which memory reservations for an overflow transaction are recorded. The method includes implementation of control mechanism for controlling concurrency between overflowing and non-overflowing transactions requested by processor devices in the multiprocessing system, the method enabling only one overflowing transaction to execute at a time in the multiprocessing system.

Abstract: A system for thread-level speculation includes a memory system for storing a program code, a plurality of registers corresponding to one or more execution contexts, for storing sets of memory addresses that are accessed speculatively, and a plurality of processors, each providing the one or more execution contexts, in communication with the memory system, wherein a processor of the plurality of processors executes the program code to implement method steps of dividing a program into a plurality of epochs to be executed in parallel by the system, wherein one of the epochs is executed non-speculatively and the other epochs are executed speculatively, determining a current epoch to be executed on an execution context, encoding addresses read during execution of the current epoch, encoding addresses written during execution of predecessor epochs of the current epoch, and encoding addresses written during execution of successor epochs of the current epoch.

Abstract: A method and apparatus for conditional memory ordering are disclosed. The cost of memory ordering is reduced by determining circumstances in which a memory ordering operation is unnecessary and avoiding the overheads of these operations by reducing the frequency of invoking hardware memory ordering mechanisms. Hardware instructions for implementing a conditional memory ordering method and apparatus is described which may be implemented in a multiprocessor environment. The conditional memory ordering instruction executes locally using a release vector containing release numbers for each processor in the system. The instruction first determines whether a processor identifier of the release number is associated with the current processor. Where it is not, a conditional register is examined and appropriate remote synchronization operations are commanded where necessary.

Abstract: A system and method to trigger synchronization and validation actions at memory access, in one aspect, identifies a storage class associated with a region of shared memory being accessed by a thread, determines whether the thread holds the storage class and acquires the storage class if the thread does not hold the storage class, identifies a programmable action associated with the storage class and the thread, and triggers the programmable action. One or more storage classes are respectively associated with one or more regions of shared memory. An array of storage classes associated with a thread holds one or more storage classes acquired by the thread. A configurable action table associated with a thread indicates one or more programmable actions associated with a storage class.

Abstract: A method for executing an atomic transaction includes receiving the atomic transaction at a processor for execution, determining a transactional memory location needed in memory for the atomic transaction, reserving the transactional memory location while all computation and store operations of the atomic transaction are deferred, and performing the computation and store operations, wherein the atomic transaction cannot be aborted after the reservation, and further wherein the store operation is directly committed to the memory without being buffered.

Abstract: A method and a system for implementing concurrent producer-consumer buffers are provided. The method and system in one aspect uses separate locks, one for putter and another for taker threads operating on a concurrent producer-consumer buffer. The locks operate independently of a notify-wait process.

Abstract: A method of optimizing memory synchronization through software in a multi-threaded computer system using a read-initiated memory synchronization process is described. One or more embodiments of the invention may operate in a computer system capable of executing at least one computational activity needing exclusive access shared memory. In the method of one or more embodiments, a multi-field lock may be associated with shared memory to reserved it for exclusive use by a first processor, and where the multi-field lock is already reserved by a second processor, synchronizing the shared memory by the second processor, updating the multi-field lock reservation information; and performing instruction synchronization for the first processor.

Abstract: A method and apparatus for conditional memory ordering are disclosed. The cost of memory ordering is reduced by determining circumstances in which a memory ordering operation is unnecessary and avoiding the overheads of these operations by reducing the frequency of invoking hardware memory ordering mechanisms. Hardware instructions for implementing a conditional memory ordering method and apparatus is described which may be implemented in a multiprocessor environment. The conditional memory ordering instruction executes locally using a release vector containing release numbers for each processor in the system. The instruction first determine whether a processor identifier of the release number is associated with the current processor. Where it is not, a conditional registered is examined and appropriate remote synchronization operations are commanded where necessary.

Abstract: A method of optimizing memory synchronization through software in a multi-threaded computer system using a read-initiated memory synchronization process is described. One or more embodiments of the invention may operate in a computer system capable of executing at least one computational activity needing exclusive access shared memory. In the method of one or more embodiments, a multi-field lock may be associated with shared memory to reserved it for exclusive use by a first processor, and where the multi-field lock is already reserved by a second processor, synchronizing the shared memory by the second processor, updating the multi-field lock reservation information; and performing instruction synchronization for the first processor.