Patents by Inventor Christoph Wilhelm Sele

Christoph Wilhelm Sele has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9305787
    Abstract: A method of manufacturing an electric component disclosed. A first electrically conducting layer including a first electrode of the electric component is formed on a substrate. An interlayer of a dielectric material is formed on the first electrically conducting layer, the dielectric material including an electrically insulating material. A further layer of a dielectric material is deposited on the interlayer of dielectric material, the further layer including a photo-patternable electrically insulating material. Both the further layer and said interlayer are structured, wherein the further layer of the dielectric material is used as a mask for the interlayer. A second electrically conducting layer including a second electrode of the electric component is then formed.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: April 5, 2016
    Assignee: Creator Technology B.V.
    Inventors: Christoph Wilhelm Sele, Monica Johanna Beenhakkers, Gerwin Hermanus Gelinck, Nicolaas Aldegonda Jan Maria Van Aerle, Hjalmar Edzer Ayco Huitema
  • Patent number: 8766244
    Abstract: Pixel control structure for use in a backplane for an electronic display, including a transistor that has a gate, a source, a drain, and an organic semiconductor element. The pixel control structure is formed by a first patterned conductive layer portion, a second patterned conductive layer portion, a dielectric layer portion, and an organic patterned semiconductive layer portion. The dielectric layer portion comprises an overlap region defined by overlap of the second conductive layer portion over the first conductive layer portion. The overlap region defines an overlap boundary, defined by an edge portion of the first patterned conductive layer portion and an edge portion of the second patterned conductive layer portion. The patterned semiconductive layer portion extends over the overlap region and away from the overlap region so as to extend from both first and second edge portions.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: July 1, 2014
    Assignee: Creator Technology B.V.
    Inventors: Nick A. J. M. van Aerle, Erik van Veenendaal, Pieter van Lieshout, Christoph Wilhelm Sele, Joris P. V. Maas
  • Publication number: 20140120721
    Abstract: A method of manufacturing an electric component disclosed. A first electrically conducting layer including a first electrode of the electric component is formed on a substrate. An interlayer of a dielectric material is formed on the first electrically conducting layer, the dielectric material including an electrically insulating material. A further layer of a dielectric material is deposited on the interlayer of dielectric material, the further layer including a photo-patternable electrically insulating material. Both the further layer and said interlayer are structured, wherein the further layer of the dielectric material is used as a mask for the interlayer. A second electrically conducting layer including a second electrode of the electric component is then formed.
    Type: Application
    Filed: December 19, 2013
    Publication date: May 1, 2014
    Applicant: Creator Technology B. V.
    Inventors: Christoph Wilhelm SELE, Monica Johanna BEENHAKKERS, Gerwin Hermanus GELINCK, Nicollaas Aldegonda Jan Maria VAN AERLE, Hjalmar Edzer Ayco HUITEMA
  • Publication number: 20140091339
    Abstract: A semiconductor device having a substrate is disclosed. The substrate includes a first set of inner edges and a second set of inner edges cooperating with the first set of inner edges. The second set of inner edges is positioned outside the first set of inner edges with respect to a cavity formed by the first inner edges and the second inner edges by a pre-defined distance. The substrate further includes a layer within the cavity, including a dried liquid material formed from a liquid deposited within the cavity. The layer within the cavity is formed between the respective first inner edges and the second inner edges. The semiconductor device may be implemented in a display of an electronic device.
    Type: Application
    Filed: December 6, 2013
    Publication date: April 3, 2014
    Inventors: Christoph Wilhelm SELE, Nicolaas Aldegonda Jan Maria VAN AERLE, Eduard Jacobus Antonius LASSAUW
  • Patent number: 8686530
    Abstract: An electronic component, notably one including, for example, a TFT, a storage capacitor, or a crossing between electrically conductive layers of a stack device is disclosed. The electronic component comprises a substrate whereon a first electrically conductive layer forming electrode is provided. A second electrode formed by a second electrically conductive layer is separated from the first electrode by at least a dielectric layer, comprising an interlayer of an electrically insulating material, preferably having high resistance against electrical breakdown and a further layer of a photo-patternable electrically insulating material.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: April 1, 2014
    Assignee: Creator Technology B.V.
    Inventors: Christoph Wilhelm Sele, Monica Johanna Beenhakkers, Gerwin Hermanus Gelinck, Nicolaas Aldegonda Jan Maria Van Aerle, Hjalmar Edzer Ayco Huitema
  • Publication number: 20140027717
    Abstract: Pixel control structure for use in a backplane for an electronic display, including a transistor that has a gate, a source, a drain, and an organic semiconductor element. The pixel control structure is formed by a first patterned conductive layer portion, a second patterned conductive layer portion, a dielectric layer portion, and an organic patterned semiconductive layer portion. The dielectric layer portion comprises an overlap region defined by overlap of the second conductive layer portion over the first conductive layer portion. The overlap region defines an overlap boundary, defined by an edge portion of the first patterned conductive layer portion and an edge portion of the second patterned conductive layer portion. The patterned semiconductive layer portion extends over the overlap region and away from the overlap region so as to extend from both first and second edge portions.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 30, 2014
    Applicant: Polymer Vision B.V.
    Inventors: Nick A.J.M. van Aerle, Erik Van Veenendaal, Pieter Van Lieshout, Christoph Wilhelm Sele, Joris P.V. Maas
  • Patent number: 8603922
    Abstract: A method is described for manufacturing a semiconductor device that comprises the steps of providing on a substrate a layer of a conducting material in a pattern comprising isolated elements having a first set of edges. The method further includes providing, on the substrate, a series of wall structures for forming one or more cavities there between. The wall structures have a second set of edges cooperating with the first set of edges. The second set of edges is positioned outside the first set of edges by a pre-defined distance. The method furthermore includes depositing a liquid material in the cavities. A display and an electronic apparatus incorporating the above described features is also disclosed.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: December 10, 2013
    Assignee: Creator Technology B.V.
    Inventors: Christoph Wilhelm Sele, Nicolaas Aldegonda Jan Maria van Aerle, Eduard Jacobus Antonius Lassauw
  • Patent number: 8536579
    Abstract: The invention relates to an electronic device including a sequence of a first thin film transistor (TFT) and a second TFT, the first TFT including a first set of electrodes separated by a first insulator, the second TFT comprising a second set of electrodes separated by a second insulator, wherein the first set of electrodes and the second set of electrodes are formed from a first shared conductive layer and a second shared conductive layer, the first insulator and the second insulator being formed by a shared dielectric layer. The invention further relates to a method of manufacturing an electronic device.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: September 17, 2013
    Assignee: Creator Technology B.V.
    Inventors: Christoph Wilhelm Sele, Monica Johanna Beenhakkers, Gerwin Hermanus Gelinck, Nicolaas Aldegonda Jan Maria Van Aerle, Hjalmar Edzer Ayco Huitema
  • Publication number: 20110180785
    Abstract: A transistor structure is described herein that includes a semiconductor layer and a dielectric layer. In accordance with the disclosure, at least one of the semiconductor layer and/or the dielectric layer comprises a chemical additive having a higher reaction potential for a chemical species present in an environment than a material of the semiconductor layer and/or the dielectric layer.
    Type: Application
    Filed: January 27, 2010
    Publication date: July 28, 2011
    Inventors: Christoph Wilhelm Sele, Kevin Michael O'Neill, Nicolaas Aldegonda Jan Maria van Aerle
  • Publication number: 20110180816
    Abstract: A method is described for manufacturing a semiconductor device that comprises the steps of providing on a substrate a layer of a conducting material in a pattern comprising isolated elements having a first set of edges. The method further includes providing, on the substrate, a series of wall structures for forming one or more cavities there between. The wall structures have a second set of edges cooperating with the first set of edges. The second set of edges is positioned outside the first set of edges by a pre-defined distance. The method furthermore includes depositing a liquid material in the cavities. A display and an electronic apparatus incorporating the above described features is also disclosed.
    Type: Application
    Filed: January 27, 2010
    Publication date: July 28, 2011
    Inventors: Christoph Wilhelm Sele, Nicolaas Aldegonda Jan Maria van Aerle, Eduard Jacobus Antonius Lassauw
  • Publication number: 20100320448
    Abstract: An electronic component, notably one including, for example, a TFT, a storage capacitor, or a crossing between electrically conductive layers of a stack device is disclosed. The electronic component comprises a substrate whereon a first electrically conductive layer forming electrode is provided. A second electrode formed by a second electrically conductive layer is separated from the first electrode by at least a dielectric layer, comprising an interlayer of an electrically insulating material, preferably having high resistance against view (a) electrical breakdown and a further layer of a photo-patternable electrically insulating material.
    Type: Application
    Filed: July 16, 2008
    Publication date: December 23, 2010
    Applicant: Polymer Vision Limited
    Inventors: Christoph Wilhelm Sele, Monica Johanna Beenhakkers, Gerwin Hermanus Gelinck, Nicolaas Aldegonda Jan Maria van Aerle, Hjalmar Edzer Ayco Huitema
  • Publication number: 20100237352
    Abstract: The invention relates to an electronic device comprising a sequence of a first thin film transistor (TFT) and a second TFT, the first TFT comprising a first set of electrodes separated by a first insulator, the second TFT comprising a second set of electrodes separated by a second insulator, wherein the first set of electrodes and the second set of electrodes are formed from a first shared conductive layer and a second shared conductive layer, the first insulator and the second insulator being formed by a shared dielectric layer. The invention further relates to a method of manufacturing an electronic device.
    Type: Application
    Filed: July 16, 2008
    Publication date: September 23, 2010
    Inventors: Christoph Wilhelm Sele, Monica Johanna Beenhakkers, Gerwin Hermanus Gelinck, Nicolaas Aldegonda Jan Maria Van Aerle, Hjalmar Edzer Ayco Huitema
  • Patent number: 7407849
    Abstract: A method for forming an organic or partly organic switching device. The method comprises depositing layers of conducing, semiconducting and/or insulating layers by solution processing and direct printing. Then, high-resolution patterns of electroactive polymers are formed by self-aligned formation of a surface energy barrier around a first pattern that repels the solution of a second material.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: August 5, 2008
    Assignees: Plastic Logic Limited, Cambridge University Technical Services Limited
    Inventors: Henning Sirringhaus, Michael J. Banach, Nicholas Jim Stone, David William Joseph Wilson, John Devin Mackenzie, Wilhelmus Theodorus Stefanus Huck, Christoph Wilhelm Sele