Patents by Inventor Christophe Berthelot
Christophe Berthelot has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11601650Abstract: Dynamically allocating virtual or physical CPU cycles for use in processing a video stream. Video complexity information for two or more digital video streams actively being processed by one or more video encoders is determined at periodic intervals. Video complexity information describes the complexity of digital video carried by the digital video streams across a bounded number of consecutive digital frames which includes digital frames not yet processed by the one or more video encoders. A determination is made as to whether a number of CPU cycles allocated for processing a particular digital video stream should be adjusted based on the determined video complexity information. The number of CPU cycles allocated for processing the particular digital video stream may be dynamically adjusted by changing an amount of CPU cycles allocated to a virtual machine in which the stream is processed or by processing the stream in a different virtual machine.Type: GrantFiled: January 19, 2021Date of Patent: March 7, 2023Assignee: Harmonic, Inc.Inventors: Neven Haltmayer, Eric Le Bars, Arnaud Mahe, Christophe Berthelot, David Henry, Jeremy C. Rosenberg
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Publication number: 20210144380Abstract: Dynamically allocating virtual or physical CPU cycles for use in processing a video stream. Video complexity information for two or more digital video streams actively being processed by one or more video encoders is determined at periodic intervals. Video complexity information describes the complexity of digital video carried by the digital video streams across a bounded number of consecutive digital frames which includes digital frames not yet processed by the one or more video encoders. A determination is made as to whether a number of CPU cycles allocated for processing a particular digital video stream should be adjusted based on the determined video complexity information. The number of CPU cycles allocated for processing the particular digital video stream may be dynamically adjusted by changing an amount of CPU cycles allocated to a virtual machine in which the stream is processed or by processing the stream in a different virtual machine.Type: ApplicationFiled: January 19, 2021Publication date: May 13, 2021Inventors: Neven Haltmayer, Eric Le Bars, Arnaud Mahe, Christophe Berthelot, David Henry, Jeremy C. Rosenberg
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Patent number: 11006137Abstract: A scheduler of computer processes. The scheduler obtains predictions of a computing load of at least one multimedia process comprising real time video encoding or transcoding of a video in real time, including predictions of a target index of video quality to deliver the video over a period of time. Predictions of available computing capacities of a cluster are also retrieved. A determination is made, based on the predictions of the computing load and the predictions of the available computing capacities, of a processing capability to allocate the at least one multimedia process during the period of time. At least one virtual environment is created for the at least one multimedia process. The computing capacity of the at least one virtual environment is adapted to the predictions of the computing load of the at least one multimedia process during the period of time.Type: GrantFiled: February 25, 2019Date of Patent: May 11, 2021Assignee: Harmonic, Inc.Inventors: Eric Le Bars, Arnaud Mahe, Christophe Berthelot
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Patent number: 10897616Abstract: Approaches for dynamically allocating CPU cycles for use in processing a video stream. Video complexity information for two or more digital video streams actively being processed by one or more video encoders is determined at periodic intervals. Video complexity information describes the complexity of digital video carried by the digital video streams across a bounded number of consecutive digital frames which includes digital frames not yet processed by the one or more video encoders. A determination is made as to whether a number of CPU cycles allocated for processing a particular digital video stream should be adjusted based on the determined video complexity information. The number of CPU cycles allocated for processing the particular digital video stream may be dynamically adjusted by changing an amount of CPU cycles allocated to a virtual machine in which the stream is processed or by processing the stream in a different virtual machine.Type: GrantFiled: October 15, 2018Date of Patent: January 19, 2021Assignee: Harmonic, Inc.Inventors: Neven Haltmayer, Eric Le Bars, Arnaud Mahe, Christophe Berthelot, David Henry, Jeremy Rosenberg
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Publication number: 20190222857Abstract: A scheduler of computer processes. The scheduler obtains predictions of a computing load of at least one multimedia process comprising real time video encoding or transcoding of a video in real time, including predictions of a target index of video quality to deliver the video over a period of time. Predictions of available computing capacities of a cluster are also retrieved. A determination is made, based on the predictions of the computing load and the predictions of the available computing capacities, of a processing capability to allocate the at least one multimedia process during the period of time. At least one virtual environment is created for the at least one multimedia process. The computing capacity of the at least one virtual environment is adapted to the predictions of the computing load of the at least one multimedia process during the period of time.Type: ApplicationFiled: February 25, 2019Publication date: July 18, 2019Inventors: Eric Le Bars, Arnaud Mahe, Christophe Berthelot
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Patent number: 10216541Abstract: A scheduler of computer processes. The scheduler comprises first processing logic configured to obtain predictions of a computing load of a computer process to allocate. Predictions are associated with a period of time. The processing logic retrieves predictions of available computing capacities for the period of time, and determines, based on the predictions, a processing capability to allocate at least one computer process during the period of time. The scheduler may comprise second processing logic configured to create at least one Operating-System-Level virtual environment, for a computer program, that has a computing capacity equal to or higher than the predicted computing load of at least one computer process to allocate at a start of the period of time. The second processing logic may adapt the computing capacity of an Operating-System-Level virtual environment to the predictions of the computing load of at least one computer process during the period of time.Type: GrantFiled: December 27, 2016Date of Patent: February 26, 2019Assignee: Harmonic, Inc.Inventors: Eric Le Bars, Arnaud Mahe, Christophe Berthelot
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Publication number: 20190052880Abstract: Approaches for dynamically allocating CPU cycles for use in processing a video stream. Video complexity information for two or more digital video streams actively being processed by one or more video encoders is determined at periodic intervals. Video complexity information describes the complexity of digital video carried by the digital video streams across a bounded number of consecutive digital frames which includes digital frames not yet processed by the one or more video encoders. A determination is made as to whether a number of CPU cycles allocated for processing a particular digital video stream should be adjusted based on the determined video complexity information. The number of CPU cycles allocated for processing the particular digital video stream may be dynamically adjusted by changing an amount of CPU cycles allocated to a virtual machine in which the stream is processed or by processing the stream in a different virtual machine.Type: ApplicationFiled: October 15, 2018Publication date: February 14, 2019Inventors: Neven Haltmayer, Eric Le Bars, Arnaud Mahe, Christophe Berthelot, David Henry, Jeremy Rosenberg
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Patent number: 10133605Abstract: The estimation of a computing capacity of a machine. The computing capacity is estimated by iteratively adding and removing calibrated computer processes on the machine, and performing a sum of computing loads of processes that execute on the machine. In order to characterize the ability of a machine to run in parallel a number of processes having a defined computing load, the processes are associated to a condition of success.Type: GrantFiled: September 10, 2016Date of Patent: November 20, 2018Assignee: Harmonic, Inc.Inventors: Eric Le Bars, Arnaud Mahe, Christophe Berthelot, David Henry
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Publication number: 20170185450Abstract: A scheduler of computer processes. The scheduler comprises first processing logic configured to obtain predictions of a computing load of a computer process to allocate. Predictions are associated with a period of time. The processing logic retrieves predictions of available computing capacities for the period of time, and determines, based on the predictions, a processing capability to allocate at least one computer process during the period of time. The scheduler may comprise second processing logic configured to create at least one Operating-System-Level virtual environment, for a computer program, that has a computing capacity equal to or higher than the predicted computing load of at least one computer process to allocate at a start of the period of time. The second processing logic may adapt the computing capacity of an Operating-System-Level virtual environment to the predictions of the computing load of at least one computer process during the period of time.Type: ApplicationFiled: December 27, 2016Publication date: June 29, 2017Inventors: Eric Le Bars, Arnaud Mahe, Christophe Berthelot
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Publication number: 20170075731Abstract: The estimation of a computing capacity of a machine. The computing capacity is estimated by iteratively adding and removing calibrated computer processes on the machine, and performing a sum of computing loads of processes that execute on the machine. In order to characterize the ability of a machine to run in parallel a number of processes having a defined computing load, the processes are associated to a condition of success.Type: ApplicationFiled: September 10, 2016Publication date: March 16, 2017Inventors: Eric Le Bars, Arnaud Mahe, Christophe Berthelot, David Henry
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Publication number: 20150063444Abstract: The invention relates to a method for dynamic quantization of an image stream including transformed blocks, the method comprising a step for establishing a relationship (V12, V10, V20) between at least one temporal predictive encoding source block (330, 323) of a first image (B1, P2) and one or more reference blocks (311, 312, 313, 314, 316, 321, 322, 323, 324) belonging to other images (I0, P2), the method comprising, for at least one of said transformed blocks, a step of quantization of said block wherein the level of quantization applied to this block is chosen (402) at least partly as a function of the relationship or relationships (V12, V10, V20) established between this block and blocks belonging to other images. The invention applies notably to the improvement of video compression in order to improve the visual rendition of encoded videos.Type: ApplicationFiled: April 11, 2013Publication date: March 5, 2015Inventors: Stephane Allie, Marc Amstoutz, Christophe Berthelot
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Publication number: 20040174908Abstract: A method is disclosed for splicing digital signals comprising packets of complete data and differential data at the transmission stage, especially MPEG-2 signals. The major reactions are those of erroneous reactions of the standardized decoder (T-STD) owing to the splicing. A splicing method is disclosed, comprising the following steps: receiving a first digital signal s1; receiving a second digital signal s2; receiving a splicing command Cc(T0); transmitting the first signal s1 before the splicing indicated by the splicing command Cc(T0), and transmitting the second signal s2 after the splicing indicated by the splicing command Cc(T0); wherein the transmission of the second signal s2 starts with the I or P packets of complete data closest to the instant To indicated by the splicing command Cc(T0) in such a way that the reproduction of the second signal s2 starts with the reproduction of the I or P packet of complete data.Type: ApplicationFiled: December 12, 2003Publication date: September 9, 2004Inventors: Eric Le Bars, Christophe Berthelot, Samuel Vermeulen