Abstract: A regenerative frequency divider comprising an in-phase mixer circuit and a phase-shifted mixer circuit. At least one switching device of the in-phase mixer circuit is of a smaller scale than a corresponding switching device of the transconductance component of the in-phase mixer circuit. In some examples, at least one switching device within an input switching stage of the regenerative frequency divider forming part of the phase-shifted mixer circuit is of a smaller scale than a respective corresponding switching device within the input switching stage forming part of the in-phase mixer circuit. In some further examples, all switching devices within the phase-shifted mixer circuit are of a small scale than respective corresponding switching devices within the in-phase mixer circuit.

Abstract: A regenerative frequency divider comprising an in-phase mixer circuit and a phase-shifted mixer circuit. At least one switching device of the in-phase mixer circuit is of a smaller scale than a corresponding switching device of the transconductance component of the in-phase mixer circuit. In some examples, at least one switching device within an input switching stage of the regenerative frequency divider forming part of the phase-shifted mixer circuit is of a smaller scale than a respective corresponding switching device within the input switching stage forming part of the in-phase mixer circuit. In some further examples, all switching devices within the phase-shifted mixer circuit are of a small scale than respective corresponding switching devices within the in-phase mixer circuit.

Abstract: A circuit includes an output node; a first current source coupled via at least one first switch to at least the output node and a calibration node, wherein the first switch alternately operably couples the first current source to the output node or the calibration node; a second current source of opposing polarity to the first current source and operably coupled via at least one second switch to at least the output node and the calibration node, wherein the second switch alternately operably couples the second current source to the output node or the calibration node; and a current control circuit having an adjustment circuit operably coupled to the calibration node, wherein the current control circuit couples both the first and second current sources to the calibration node when a current from the first/second current source is not to be used as an output from the output node.

Abstract: A counter/divider where the counter/divider comprises a: a pre-scaler operable in a first mode to divide an input signal by M and in a second mode to divide the input signal by N, where N is greater than M; a first programmable counter, and a second programmable counter; and where the first and second programmable counters are responsive to an output of the pre-scaler and an output of the first counter controls whether the pre-scaler operates in the first mode or the second mode, wherein the first counter is operable to count to greater than one.

Abstract: A counter/divider where the counter/divider comprises a: a pre-scaler operable in a first mode to divide an input signal by M and in a second mode to divide the input signal by N, where N is greater than M; a first programmable counter, and a second programmable counter; and where the first and second programmable counters are responsive to an output of the pre-scaler and an output of the first counter controls whether the pre-scaler operates in the first mode or the second mode, wherein the first counter is operable to count to greater than one.

Abstract: A charge pump circuit is disclosed that includes a positive current output circuit for providing a positive current to an output of the charge pump circuit, a negative current output circuit for providing a negative current to the output of the charge pump circuit, and a calibration unit for permitting the charge pump circuit to be adjusted to reduce any current mismatch between the positive and negative currents and to provide that any current mismatch is integrated into a PLL loop filter capacitance.

Abstract: A receiver circuit is disclosed for use in a communication system. The receiver circuit includes a forward path with a channel selection filter and a feedback path. The output of the channel selection filter is provided to an output device. The feedback path includes a feedback filter and a mixer. The input of the feedback filter is coupled to the output of the channel selection filter and the output of the feedback filter is coupled to a first input of the mixer. The second input of the mixer is coupled to a multi-frequency signal generator, and the output of the mixer is coupled to the forward path of the receiver circuit.

Abstract: A charge pump circuit is disclosed that includes a positive current output circuit for providing a positive current to an output of the charge pump circuit, a negative current output circuit for providing a negative current to the output of the charge pump circuit, and a calibration unit for permitting the charge pump circuit to be adjusted to reduce any current mismatch between the positive and negative currents and to provide that any current mismatch is integrated into a PLL loop filter capacitance.