Patents by Inventor Christophe Chanussot
Christophe Chanussot has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9595316Abstract: Embodiments of design-for-test (DFT) apparatuses and related techniques are disclosed herein. In some embodiments, a DFT apparatus may include an SRAM cell, read/write (R/W) circuitry to provide a nominal word line (WL) voltage and a nominal BL voltage for application to the SRAM cell during accesses. The DFT apparatus may also include test circuitry having an activated state and a deactivated state. When the test circuitry is in the activated state, in some embodiments, the WL voltage and/or the BL voltage applied to the SRAM cell may be different from the nominal voltages provided by the R/W/decoder circuitry. The R/W/decoder circuitry may be operated to perform accesses to the SRAM cell while the test circuitry is in the activated state. Other embodiments may be disclosed and/or claimed.Type: GrantFiled: November 24, 2015Date of Patent: March 14, 2017Assignee: INTEL IP CORPORATIONInventors: Vianney Choserot, Loubna Hannati, Nabil Badereddine, Christophe Chanussot
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Publication number: 20160078927Abstract: Embodiments of design-for-test (DFT) apparatuses and related techniques are disclosed herein. In some embodiments, a DFT apparatus may include an SRAM cell, read/write (R/W) circuitry to provide a nominal word line (WL) voltage and a nominal BL voltage for application to the SRAM cell during accesses. The DFT apparatus may also include test circuitry having an activated state and a deactivated state. When the test circuitry is in the activated state, in some embodiments, the WL voltage and/or the BL voltage applied to the SRAM cell may be different from the nominal voltages provided by the R/W/decoder circuitry. The R/W/decoder circuitry may be operated to perform accesses to the SRAM cell while the test circuitry is in the activated state. Other embodiments may be disclosed and/or claimed.Type: ApplicationFiled: November 24, 2015Publication date: March 17, 2016Applicant: INTEL IP CORPORATIONInventors: Vianney Choserot, Loubna Hannati, Nabil Badereddine, Christophe Chanussot
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Patent number: 9236144Abstract: Embodiments of design-for-test (DFT) apparatuses and related techniques are disclosed herein. In some embodiments, a DFT apparatus may include a static random access memory (SRAM) cell, read/write/decoder (R/W/decoder) circuitry to provide a nominal word line (WL) voltage and a nominal bit line (BL) voltage for application to the SRAM cell during accesses. The DFT apparatus may also include test circuitry having an activated state and a deactivated state. When the test circuitry is in the activated state, in some embodiments, the WL voltage and/or the BL voltage applied to the SRAM cell may be different from the nominal voltages provided by the R/W/decoder circuitry. The R/W/decoder circuitry may be operated to perform accesses to the SRAM cell while the test circuitry is in the activated state. Other embodiments may be disclosed and/or claimed.Type: GrantFiled: March 12, 2014Date of Patent: January 12, 2016Assignee: INTEL IP CORPORATIONInventors: Vianney Choserot, Loubna Hannati, Nabil Badereddine, Christophe Chanussot
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Publication number: 20150262707Abstract: Embodiments of design-for-test (DFT) apparatuses and related techniques are disclosed herein. In some embodiments, a DFT apparatus may include a static random access memory (SRAM) cell, read/write/decoder (R/W/decoder) circuitry to provide a nominal word line (WL) voltage and a nominal bit line (BL) voltage for application to the SRAM cell during accesses. The DFT apparatus may also include test circuitry having an activated state and a deactivated state. When the test circuitry is in the activated state, in some embodiments, the WL voltage and/or the BL voltage applied to the SRAM cell may be different from the nominal voltages provided by the R/W/decoder circuitry. The R/W/decoder circuitry may be operated to perform accesses to the SRAM cell while the test circuitry is in the activated state. Other embodiments may be disclosed and/or claimed.Type: ApplicationFiled: March 12, 2014Publication date: September 17, 2015Inventors: Vianney Choserot, Loubna Hannati, Nabil Badereddine, Christophe Chanussot
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Publication number: 20090086554Abstract: A method for operating a semiconductor memory cell is disclosed. A first voltage is applied to the memory cell. The first voltage is dependent on temperature and semiconductor process variation in a manner that keeps the memory cell in a stable region of operation.Type: ApplicationFiled: September 28, 2007Publication date: April 2, 2009Inventors: Christophe Chanussot, Vincent Gouin
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Patent number: 7492626Abstract: A memory comprises a bitline, an accessible memory element, an activable switch coupled between the bitline and the access node and a controller configured to activate the activable switch within a first activation period, to activate the activable switch within a second activation period and to deactivate the activable switch at least once when accessing to the accessible memory element during the same access operation.Type: GrantFiled: August 4, 2006Date of Patent: February 17, 2009Assignee: Infineon Technologies AGInventors: Christophe Chanussot, Vincent Gouin
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Patent number: 7486540Abstract: Method and memory device for reliably writing an information value to a memory element of the memory device. A first information value is represented by a first potential and a second information value is represented by a second potential. A bit line is provided for writing either the first information value or the second information value to the memory element. A potential controller is coupled to the bit line, where the potential controller is configured to apply a third potential to the bit line, which is less than the first potential when writing the first information value to the memory element.Type: GrantFiled: October 26, 2006Date of Patent: February 3, 2009Assignee: Infineon Technologies AGInventors: Vincent Gouin, Christophe Chanussot
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Patent number: 7394682Abstract: A bit line dummy core-cell comprises at least a first inverter and at least a second inverter which are cross coupled to form a bistable flip-flop. The first inverter comprises a first PMOS transistor and a first NMOS transistor connected in series by means of a first internal storage node between a high reference potential and a low reference potential. The second inverter comprises a second PMOS transistor and a second NMOS transistor connected in series by means of a second internal storage node. The source of the second PMOS transistor and the second internal storage node are connected to the low reference potential so that the first internal storage node always stores a logic high level. A first access transistor is coupled between a dummy bit line providing a self-timing signal and the first internal node storing the logical high level.Type: GrantFiled: October 25, 2006Date of Patent: July 1, 2008Assignee: Infineon Technologies AGInventors: Martin Ostermayr, Christophe Chanussot, Vincent Gouin, Alexander Olbrich
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Publication number: 20080112245Abstract: A bit line dummy core-cell comprises at least a first inverter and at least a second inverter which are cross coupled to form a bistable flip-flop. The first inverter comprises a first PMOS transistor and a first NMOS transistor connected in series by means of a first internal storage node between a high reference potential and a low reference potential. The second inverter comprises a second PMOS transistor and a second NMOS transistor connected in series by means of a second internal storage node. The source of the second PMOS transistor and the second internal storage node are connected to the low reference potential so that the first internal storage node always stores a logic high level. A first access transistor is coupled between a dummy bit line providing a self-timing signal and the first internal node storing the logical high level.Type: ApplicationFiled: October 25, 2006Publication date: May 15, 2008Inventors: Martin Ostermayr, Christophe Chanussot, Vincent Gouin, Alexander Olbrich
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Patent number: 7355915Abstract: The inventive memory circuit comprises a plurality of memory cells. The memory circuit further comprises a memory access means being controlled by at least one control signal. In addition, a control means for generating the at least one control signal is contained in the memory circuit, with the control means comprising a delay means. The delay means delays a switching of the at least one control signal. The delay time is adjustable in view of the applied supply voltage.Type: GrantFiled: August 24, 2005Date of Patent: April 8, 2008Assignee: Infineon Technologies AGInventors: Vincent Gouin, Jean-Patrice Coste, Christophe Chanussot
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Publication number: 20070109878Abstract: Method and memory device for reliably writing an information value to a memory element of the memory device. A first information value is represented by a first potential and a second information value is represented by a second potential. A bit line is provided for writing either the first information value or the second information value to the memory element. A potential controller is coupled to the bit line, where the potential controller is configured to apply a third potential to the bit line, which is less than the first potential when writing the first information value to the memory element.Type: ApplicationFiled: October 26, 2006Publication date: May 17, 2007Inventors: Vincent Gouin, Christophe Chanussot
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Publication number: 20070030722Abstract: A memory comprises a bitline, an accessible memory element, an activable switch coupled between the bitline and the access node and a controller configured to activate the activable switch within a first activation period, to activate the activable switch within a second activation period and to deactivate the activable switch at least once when accessing to the accessible memory element during the same access operation.Type: ApplicationFiled: August 4, 2006Publication date: February 8, 2007Inventors: Christophe Chanussot, Vincent Gouin
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Publication number: 20060050572Abstract: The inventive memory circuit comprises a plurality of memory cells. The memory circuit further comprises a memory access means being controlled by at least one control signal. In addition, a control means for generating the at least one control signal is contained in the memory circuit, with the control means comprising a delay means. The delay means delays a switching of the at least one control signal. The delay time is adjustable in view of the applied supply voltage.Type: ApplicationFiled: August 24, 2005Publication date: March 9, 2006Inventors: Vincent Gouin, Jean-Patrice Coste, Christophe Chanussot