Patents by Inventor Christophe de Dinechin
Christophe de Dinechin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8694819Abstract: A system and corresponding method virtualizes a real-time clock in the presence of a time-disrupting event. The real-time clock is used with physical machines and includes a single time source within each of the physical machines. The system is implemented in one or more programmable devices, which may be hardware and/or software devices, or a combination of hardware and software devices. The physical machines include one or more virtual machines. The system includes an offset module that determines a time difference offset between a virtual interrupt timer counter (ITCV) associated with a virtual machine and a physical interrupt timer counter (ITCP) associated with a physical machine. The system also includes a virtual machine monitor that computes one or more first time adjustments based on the offset and applies the adjustments to eliminate at least a first part of the offset.Type: GrantFiled: August 24, 2009Date of Patent: April 8, 2014Assignee: Hewlett-Packard Development Company, L.P.Inventors: Christophe De Dinechin, Karen Lee Noel, Jonathan Ross
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Patent number: 8505020Abstract: An event calling for a migration of a workload from a source processor set of processing units to a target processor set of processing units is detected. Processes of the workload are allocated to a second processor set of processing units so that some workload processes are executed on the source processor set and some workload processes are executed on a second processor set of processor units. Then, some workload processes are allocated to the second processor set so that no workload process is executing on the source processor set and at least some of said processes are executing on the second process set. The second processor set can be the target processor set or an intermediate processor set from which the workload is migrated to the target processor set.Type: GrantFiled: August 29, 2010Date of Patent: August 6, 2013Assignee: Hewlett-Packard Development Company, L.P.Inventors: Christophe de Dinechin, Dale C. Morris, Patrick Knebel, Russ W. Herrell
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Publication number: 20120054766Abstract: An event calling for a migration of a workload from a source processor set of processing units to a target processor set of processing units is detected. Processes of the workload are allocated to a second processor set of processing units so that some workload processes are executed on the source processor set and some workload processes are executed on a second processor set of processor units. Then, some workload processes are allocated to the second processor set so that no workload process is executing on the source processor set and at least some of said processes are executing on the second process set. The second processor set can be the target processor set or an intermediate processor set from which the workload is migrated to the target processor set.Type: ApplicationFiled: August 29, 2010Publication date: March 1, 2012Inventors: Christophe de Dinechin, Dale C. Morris, Patrick Knebel, Russ W. Herrell
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Patent number: 8091090Abstract: In one embodiment of the present invention, a virtual-machine monitor detects entry and exit from guest-operating system code, storing the values of a set of high-order floating point registers in memory on entry, and restoring the values of the set of high-order floating point registers on exit. The virtual-machine monitor can then use the set of high-order floating point registers as scratch registers for emulation of guest-operating-system instructions. In alternative embodiments, a virtual-machine monitor obtains scratch registers for any code that the virtual-machine monitor can detect entry into and exit from, and for which a set of infrequently used registers can be identified, by storing the current contents of the set of registers upon detected entry into the code and restoring the original contents of the set of registers upon exit from the code.Type: GrantFiled: January 5, 2005Date of Patent: January 3, 2012Assignee: Hewlett-Packard Development Company, L.P.Inventors: Christophe de Dinechin, Todd Kjos, Jonathan Ross
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Patent number: 7996833Abstract: Various embodiments of the present invention are directed to efficient methods by which virtual-machine monitors can introduce instructions into guest-operating-system code. In one embodiment of the present invention, the virtual-machine monitor builds instructions dynamically, at insertion time, using specified values for fields within the instruction. In one embodiment of the present invention, the instructions and instruction field values are stored in an instruction-block-representing data structure.Type: GrantFiled: July 31, 2004Date of Patent: August 9, 2011Assignee: Hewlett-Packard Development Company, L.P.Inventors: Christophe de Dinechin, Todd Kjos, Jonathan Ross
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Publication number: 20110047315Abstract: A system and corresponding method virtualizes a real-time clock in the presence of a time-disrupting event. The real-time clock is used with physical machines and includes a single time source within each of the physical machines. The system is implemented in one or more programmable devices, which may be hardware and/or software devices, or a combination of hardware and software devices. The physical machines include one or more virtual machines. The system includes an offset module that determines a time difference offset between a virtual interrupt timer counter (ITCV) associated with a virtual machine and a physical interrupt timer counter (ITCP) associated with a physical machine. The system also includes a virtual machine monitor that computes one or more first time adjustments based on the offset and applies the adjustments to eliminate at least a first part of the offset.Type: ApplicationFiled: August 24, 2009Publication date: February 24, 2011Inventors: Christophe De Dinechin, Karen Lee Noel, Jonathan Ross
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Patent number: 7765238Abstract: A method for mapping an active entry within a virtually hashed page table is disclosed. An active entry within a virtually hashed page table is populated. A link table for locating a link at an offset from an active entry is maintained. This link table continues to be maintained as a valid link table until an occupied head bucket threshold is exceeded or a collision has occurred.Type: GrantFiled: April 30, 2007Date of Patent: July 27, 2010Assignee: Hewlett-Packard Development Company, L.P.Inventors: Christophe De Dinechin, Todd J. Kjos, Jonathan K. Ross
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Patent number: 7613847Abstract: A computer system comprises a physical computer and a virtual machine monitor executable on the physical computer and configured to create an emulation of at least one guest operating system adapted to control the physical computer. The computer system further comprises a host executable on the physical computer that manages physical resources coupled to the physical computer on behalf of the virtual machine monitor and the at least one guest operating system. The host is adapted to virtualize a Peripheral Component Interconnect (PCI) configuration address space whereby the at least one guest operating system controls PCI input/output (I/O) devices directly and in absence of I/O emulation.Type: GrantFiled: May 16, 2006Date of Patent: November 3, 2009Assignee: Hewlett-Packard Development Company, L.P.Inventors: Todd J. Kjos, Jonathan K. Ross, Christophe De Dinechin
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Patent number: 7577944Abstract: Instructions in a first instruction stream are unbundled; certain unbundled instructions are translated; and the instructions are rebundled. Bundled instructions are used by processors based on Very Long Instruction Word (VLIW) and Explicitly Parallel Instruction Computing (EPIC) technology.Type: GrantFiled: March 18, 2002Date of Patent: August 18, 2009Assignee: Hewlett-Packard Development Company, L.P.Inventor: Christophe de Dinechin
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Patent number: 7478394Abstract: A virtual machine application interrupts execution of a host OS under software control at a predetermined interruption point, instead of interrupting the execution at an arbitrary instruction. The context of the host OS is saved by using an inconsequential register as temporary storage. Context of the host OS is restored by using an inconsequential register as temporary storage.Type: GrantFiled: June 4, 2001Date of Patent: January 13, 2009Assignee: Hewlett-Packard Development Company, L.P.Inventors: Christophe de Dinechin, Jean-Marc Chevrot
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Publication number: 20080270349Abstract: A method for mapping an active entry within a virtually hashed page table is disclosed. An active entry within a virtually hashed page table is populated. A link table for locating a link at an offset from an active entry is maintained. This link table continues to be maintained as a valid link table until an occupied head bucket threshold is exceeded or a collision has occurred.Type: ApplicationFiled: April 30, 2007Publication date: October 30, 2008Inventors: Christophe De Dinechin, Todd J. Kjos, Jonathan K. Ross
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Patent number: 7330942Abstract: Various embodiments of the present invention are directed to efficient provision, by a virtual-machine monitor, of a virtual, physical memory interface to guest operating systems and other programs and routines interfacing to a computer system through a virtual-machine interface. In one embodiment of the present invention, a virtual-machine monitor maintains control over a translation lookaside buffer (“TLB”), machine registers which control virtual memory translations, and a processor page table, providing each concurrently executing guest operating system with a guest-processor-page table and guest-physical memory-to-physical memory translations. In one embodiment, a virtual-machine monitor can rely on hardware virtual-address-translation mechanisms for the bulk of virtual-address translations needed during guest-operating-system execution, thus providing a guest-physical memory interface without introducing excessive overhead and inefficiency.Type: GrantFiled: December 29, 2004Date of Patent: February 12, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventors: Christophe de Dinechin, Todd Kjos, Jonathan Ross
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Publication number: 20080005297Abstract: A computer system comprises a physical computer and a virtual machine monitor executable on the physical computer and configured to create an emulation of at least one guest operating system adapted to control the physical computer. The computer system further comprises a host executable on the physical computer that manages physical resources coupled to the physical computer on behalf of the virtual machine monitor and the at least one guest operating system. The host is adapted to virtualize a Peripheral Component Interconnect (PCI) configuration address space whereby the at least one guest operating system controls PCI input/output (I/O) devices directly and in absence of I/O emulation.Type: ApplicationFiled: May 16, 2006Publication date: January 3, 2008Inventors: Todd J. Kjos, Jonathan K. Ross, Christophe De Dinechin
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Patent number: 7213125Abstract: Various embodiments of the present invention are directed to methods by which a virtual-machine monitor can introduce branch instructions, in order to emulate privileged and other instructions on behalf of a guest operating system, into guest-operating-system code residing on virtually aliased virtual-memory pages. In a described embodiment of the present invention, the virtual-machine monitor physically aliases each virtual alias for a particular physical memory page by allocating a physical page for the virtual alias, copying the original contents of the physical memory page to the allocated physical page, or physical alias page, and subsequently patching each physical alias page appropriate to the physical address of the physical alias page.Type: GrantFiled: July 31, 2004Date of Patent: May 1, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventors: Christophe de Dinechin, Todd Kjos, Jonathan Ross
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Publication number: 20060036830Abstract: Various embodiments of the present invention are directed to efficient methods for virtual-machine monitors to detect, at run time, initial attempts by guest operating systems and other higher-level software to access or execute particular instructions or values corresponding to the particular instructions, that, when accessed for execution, need to be emulated by a virtual-machine monitor, rather than directly accessed by guest operating systems. In certain embodiments of the present invention, the virtual-machine monitor assigns various guest-operating-system-code-containing memory pages to one of a small number of protection-key domains. By doing so, the virtual-machine monitor can arrange for any initial access to the memory pages assigned to the protection-key domains to generate a key-permission fault, after which the key-permission-fault handler of the virtual-machine monitor is invoked to arrange for subsequent, efficient access or emulation of access to the protected pages.Type: ApplicationFiled: December 22, 2004Publication date: February 16, 2006Inventors: Christophe de Dinechin, Jonathan Ross, Todd Kjos
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Publication number: 20060026383Abstract: Various embodiments of the present invention are directed to efficient provision, by a virtual-machine monitor, of a virtual, physical memory interface to guest operating systems and other programs and routines interfacing to a computer system through a virtual-machine interface. In one embodiment of the present invention, a virtual-machine monitor maintains control over a translation lookaside buffer (“TLB”), machine registers which control virtual memory translations, and a processor page table, providing each concurrently executing guest operating system with a guest-processor-page table and guest-physical memory-to-physical memory translations. In one embodiment, a virtual-machine monitor can rely on hardware virtual-address-translation mechanisms for the bulk of virtual-address translations needed during guest-operating-system execution, thus providing a guest-physical memory interface without introducing excessive overhead and inefficiency.Type: ApplicationFiled: December 29, 2004Publication date: February 2, 2006Inventors: Christophe de Dinechin, Todd Kjos, Jonathan Ross
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Patent number: 6895491Abstract: A software monitor, interposed between the hardware layer of a computer system and one or more guest operating systems, constructs and maintains a guest-physical-address-to-host-physical-address map for each guest operating system, and maintains a virtual memory addressing context for each guest operating system that may include a virtual-hash-page table for each guest operating system, the contents of translation registers for each guest operating system, CPU-specific virtual-memory translations for each guest operating system, and the contents of various status registers.Type: GrantFiled: September 26, 2002Date of Patent: May 17, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: Todd Kjos, Jonathan Ross, Christophe de Dinechin
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Publication number: 20040064668Abstract: A software monitor, interposed between the hardware layer of a computer system and one or more guest operating systems, constructs and maintains a guest-physical-address-to-host-physical-address map for each guest operating system, and maintains a virtual memory addressing context for each guest operating system that may include a virtual-hash-page table for each guest operating system, the contents of translation registers for each guest operating system, CPU-specific virtual-memory translations for each guest operating system, and the contents of various status registers.Type: ApplicationFiled: September 26, 2002Publication date: April 1, 2004Inventors: Todd Kjos, Jonathan Ross, Christophe de Dinechin
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Publication number: 20030177482Abstract: Instructions in a first instruction stream are unbundled; certain unbundled instructions are translated; and the instructions are rebundled. Bundled instructions are used by processors based on Very Long Instruction Word (VLIW) and Explicitly Parallel Instruction Computing (EPIC) technology.Type: ApplicationFiled: March 18, 2002Publication date: September 18, 2003Inventor: Christophe de Dinechin