Patents by Inventor Christophe Denis Bernard Avoinne

Christophe Denis Bernard Avoinne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • HARDWARE MANAGED POWER COLLAPSE AND CLOCK WAKE-UP FOR MEMORY MANAGEMENT UNITS AND DISTRIBUTED VIRTUAL MEMORY NETWORKS
    Publication number: 20190324512
    Abstract: Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.
    Type: Application
    Filed: July 1, 2019
    Publication date: October 24, 2019
    Inventors: Jason Edward PODAIMA, Christophe Denis Bernard AVOINNE, Manokanthan SOMASUNDARAM, Sina DENA, Paul Christopher John WIERCIENSKI, Bohuslav RYCHLIK, Steven John HALTER, Jaya Prakash SUBRAMANIAM GANASAN, Myil RAMKUMAR, Dipti Ranjan PAL
  • Hardware managed power collapse and clock wake-up for memory management units and distributed virtual memory networks
    Patent number: 10386904
    Abstract: Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: August 20, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Jason Edward Podaima, Christophe Denis Bernard Avoinne, Manokanthan Somasundaram, Sina Dena, Paul Christopher John Wiercienski, Bohuslav Rychlik, Steven John Halter, Jaya Prakash Subramaniam Ganasan, Myil Ramkumar, Dipti Ranjan Pal
  • HARDWARE MANAGED POWER COLLAPSE AND CLOCK WAKE-UP FOR MEMORY MANAGEMENT UNITS AND DISTRIBUTED VIRTUAL MEMORY NETWORKS
    Publication number: 20170285705
    Abstract: Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.
    Type: Application
    Filed: March 31, 2016
    Publication date: October 5, 2017
    Inventors: Jason Edward PODAIMA, Christophe Denis Bernard AVOINNE, Manokanthan SOMASUNDARAM, Sina DENA, Paul Christopher John WIERCIENSKI, Bohuslav RYCHLIK, Steven John HALTER, Jaya Prakash SUBRAMANIAM GANASAN, Myil RAMKUMAR, Dipt Ranjan PAL
  • Scalable Multifunction Serial Link Interface
    Publication number: 20140119463
    Abstract: An integrated circuit includes two or more communication controllers and a plurality of point to point serial communication lanes for communication external to the integrated circuit. A programmable cross-point circuit allows different sets of serial communication lanes to be coupled at different times to the communication controllers in order to optimize performance of different applications.
    Type: Application
    Filed: October 31, 2012
    Publication date: May 1, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Yves Michel Marie Masse, Eric Louis Pierre Badi, Christophe Denis Bernard Avoinne