Patents by Inventor Christophe Favergeon-Borgialli

Christophe Favergeon-Borgialli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8245011
    Abstract: Methods and systems are provided for geometry-based virtual memory management. The methods and systems use Boolean space algebra operations to manage allocation and deallocation of tiled virtual memory pages in a tiled virtual memory provided by a tiled virtual memory subsystem. A region quadtree may be maintained representing a current allocation state of tiled virtual memory pages within a container. The region quadtree may be used to locate a rectangle or two dimensional (2D) array of unallocated tiled virtual memory pages, and physical memory pages may be mapped to tiled virtual memory pages in the rectangle by updating a lookup table used to translate tiled virtual memory page addresses to physical memory page addresses. A union or intersection of region quadtrees may be performed to generate a new region quadtree representing a new current allocation state of the tiled virtual memory pages.
    Type: Grant
    Filed: December 5, 2008
    Date of Patent: August 14, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Christophe Favergeon-Borgialli, Jean-Christian Kircher, Stéphane Sintes
  • Patent number: 8200479
    Abstract: Methods and mobile devices are provided for asymmetric independent processing of audio streams in a system on a chip (SOC). More specifically, independent audio paths are provided for processors performing audio processing on the SOC and mixing of decoded audio samples from the processors is performed digitally on the SOC by a hardware digital mixer.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: June 12, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Stephane Sintes, Franck Seigneret, Christophe Favergeon-Borgialli
  • Publication number: 20090204784
    Abstract: Methods, digital systems, and computer readable media are provided for managing a tiled virtual memory by maintaining a region quadtree representing a current allocation state of tiled virtual memory pages in the tiled virtual memory.
    Type: Application
    Filed: December 5, 2008
    Publication date: August 13, 2009
    Inventors: Christophe Favergeon-Borgialli, Jean-Christian Kircher, Stephane Sintes
  • Publication number: 20090204413
    Abstract: Methods and mobile devices are provided for asymmetric independent processing of audio streams in a system on a chip (SOC). More specifically, independent audio paths are provided for processors performing audio processing on the SOC and mixing of decoded audio samples from the processors is performed digitally on the SOC by a hardware digital mixer.
    Type: Application
    Filed: December 23, 2008
    Publication date: August 13, 2009
    Inventors: Stephane Sintes, Franck Seigneret, Christophe Favergeon-Borgialli
  • Patent number: 7178138
    Abstract: The invention relates to a software system and method for automatically verifying the correct execution of an application ported from one instruction set architecture (ISA) to another ISA. In this method, versions of the application are prepared for the two ISAs. Each version is then executed in a simulator or emulator for the appropriate ISA and the results of any change in memory made during the execution are compared. If each memory change made during the execution of the target version of the application is found to be equivalent to a memory change made during the execution of the source version of the application, the execution of the target (or ported) application is verifiably correct.
    Type: Grant
    Filed: December 13, 2001
    Date of Patent: February 13, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Edward P. Kuzemchak, Christine M. Cipriani, Christophe Favergeon-Borgialli, Mary P. Luley
  • Patent number: 7162618
    Abstract: The invention relates to a method to increase the visibility of effective address computation in pipelined architectures. In this method, the current effective address delay of each instruction in the pipeline is calculated. The current effective address delay is used to determine if a valid effective address is available for each instruction. If a valid effective address for an instruction is not available, it is computed if possible.
    Type: Grant
    Filed: December 13, 2001
    Date of Patent: January 9, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Edward P. Kuzemchak, Christine M. Cipriani, Christophe Favergeon-Borgialli, Mary P. Luley
  • Publication number: 20030088855
    Abstract: The invention relates to a method to increase the visibility of effective address computation in pipelined architectures. In this method, the current effective address delay of each instruction in the pipeline is calculated. The current effective address delay is used to determine if a valid effective address is available for each instruction. If a valid effective address for an instruction is not available, it is computed if possible.
    Type: Application
    Filed: December 13, 2001
    Publication date: May 8, 2003
    Inventors: Edward P. Kuzemchak, Christine M. Cipriani, Christophe Favergeon-Borgialli, Mary P. Luley
  • Publication number: 20020184613
    Abstract: The invention relates to a software system and method for automatically verifying the correct execution of an application ported from one instruction set architecture (ISA) to another ISA. In this method, versions of the application are prepared for the two ISAs. Each version is then executed in a simulator or emulator for the appropriate ISA and the results of any change in memory made during the execution are compared. If each memory change made during the execution of the target version of the application is found to be equivalent to a memory change made during the execution of the source version of the application, the execution of the target (or ported) application is verifiably correct.
    Type: Application
    Filed: December 13, 2001
    Publication date: December 5, 2002
    Inventors: Edward P. Kuzemchak, Christine M. Cipriani, Christophe Favergeon-Borgialli, Mary P. Luley