Patents by Inventor Christophe Figuet

Christophe Figuet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11251265
    Abstract: A support for a semiconductor structure includes a charge-trapping layer on a base substrate. The charge-trapping layer consists of a polycrystalline main layer and, interposed in the main layer or between the main layer and the base substrate, at least one intermediate polycrystalline layer composed of a silicon and carbon alloy or carbon. The intermediate layer has a resistivity greater than 1000 ohm·cm.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: February 15, 2022
    Assignees: Soitec, Centre National de la Recherche Scientifiaue
    Inventors: Christophe Figuet, Oleg Kononchuk, Kassam Alassaad, Gabriel Ferro, Véronique Souliere, Christelle Veytizou, Taguhi Yeghoyan
  • Patent number: 11205702
    Abstract: A method for manufacturing a structure comprising a first substrate comprising at least one electronic component likely to be damaged by a temperature higher than 400° C. and a semiconductor layer extending on the first substrate comprises: (a) providing a first bonding metal layer on the first substrate, (b) providing a second substrate comprising successively: a semiconductor base substrate, a stack of a plurality of semiconductor epitaxial layers, a layer of SixGe1-x, with 0?x?1 being located at the surface of said stack opposite to the base substrate, and a second bonding metal layer, (c) bonding the first substrate and the second substrate through the first and second bonding metal layers at a temperature lower than or equal to 400° C., and (d) removing a part of the second substrate so as to transfer the layer of SixGe1-x on the first substrate using a selective etching process.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: December 21, 2021
    Assignee: Soitec
    Inventors: Christophe Figuet, Ludovic Ecarnot, Bich-Yen Nguyen, Walter Schwarzenbach, Daniel Delprat, Ionut Radu
  • Publication number: 20200295138
    Abstract: A method for manufacturing a structure comprising a first substrate comprising at least one electronic component likely to be damaged by a temperature higher than 400° C. and a semiconductor layer extending on the first comprises: (a) providing a first bonding metal layer on the first substrate, (b) providing a second substrate comprising successively: a semiconductor base substrate, a stack of a plurality of semiconductor epitaxial layers, a layer of SixGe1-x, with 0?x?1 being located at the surface of said stack opposite to the base substrate, and a second bonding metal layer, (c) bonding the first substrate and the second substrate through the first and second bonding metal layers at a temperature lower than or equal to 400° C., and (d) removing a part of the second substrate so as to transfer the layer of SixGe1-x on the first substrate using a selective etching process.
    Type: Application
    Filed: March 31, 2017
    Publication date: September 17, 2020
    Inventors: Christophe Figuet, Ludovic Ecarnot, Bich-Yen Nguyen, Walter Schwarzenbach, Daniel Delprat, Ionut Radu
  • Patent number: 10250282
    Abstract: A structure for radiofrequency applications includes: a semiconducting supporting substrate, and a trapping layer arranged on the supporting substrate. The trapping layer includes a higher defect density than a predetermined defect density. The predetermined defect density is the defect density beyond which the electric resistivity of the trapping layer is no lower than 10,000 ohm·cm over a temperature range extending from ?20° C. to 120° C.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: April 2, 2019
    Assignee: Soitec
    Inventors: Oleg Kononchuk, Didier Landru, Christophe Figuet
  • Publication number: 20190058031
    Abstract: A support for a semiconductor structure includes a charge-trapping layer on a base substrate. The charge-trapping layer consists of a polycrystalline main layer and, interposed in the main layer or between the main layer and the base substrate, at least one intermediate polycrystalline layer composed of a silicon and carbon alloy or carbon. The intermediate layer has a resistivity greater than 1000 ohm·cm.
    Type: Application
    Filed: February 23, 2017
    Publication date: February 21, 2019
    Applicants: Soitec, Centre National de la Recherche Scientifique, Universite Claude Bernard Lyon 1, Soitec
    Inventors: Christophe Figuet, Oleg Kononchuk, Kassam Alassaad, Gabriel Ferro, Véronique Souliere, Christelle Veytizou, Taguhi Yeghoyan
  • Patent number: 10093086
    Abstract: A process for separating at least two substrates comprising at least two separation interfaces along one of the interfaces includes, before inserting a blade between the substrate, damaging at least one portion of a peripheral region of a chosen one of the interfaces, then inserting the blade and partially parting the substrates, and applying a fluid in a space between the parted substrates while the blade remains inserted therebetween, and decreasing a rupture energy of the chosen interface by stress corrosion involving breaking of siloxane bonds present at the interface.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: October 9, 2018
    Assignee: Soitec
    Inventors: Didier Landru, Christophe Figuet
  • Publication number: 20170331501
    Abstract: A structure for radiofrequency applications includes: a semiconducting supporting substrate, and a trapping layer arranged on the supporting substrate. The trapping layer includes a higher defect density than a predetermined defect density. The predetermined defect density is the defect density beyond which the electric resistivity of the trapping layer is no lower 10,000 ohm·cm over a temperature range extending from ?20° C. to 120° C.
    Type: Application
    Filed: September 17, 2015
    Publication date: November 16, 2017
    Inventors: Oleg Kononchuk, Didier Landru, Christophe Figuet
  • Patent number: 9716029
    Abstract: A method for transferring a layer of semiconductor by providing a donor substrate that includes a useful layer of a semiconductor material, a confinement structure that includes a confinement layer of a semiconductor material having a chemical composition that is different than that of the useful layer, and two protective layers of semiconductor material that are distinct from the confinement layer with the protective layers being arranged on both sides of the confinement layer; introducing ions into a donor substrate, bonding the donor substrate to a receiver substrate, subjecting the donor and receiver substrates to a heat treatment that provides an increase in temperature during which the confinement layer attracts the ions in order to concentrate them in the confinement layer, and detaching the donor substrate from the receiver substrate by breaking the confinement layer.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: July 25, 2017
    Assignee: SOITEC
    Inventors: Fabrice Lallement, Christophe Figuet, Daniel Delprat
  • Patent number: 9646825
    Abstract: The invention relates to a method for fabricating a composite structure comprising a layer to be separated by irradiation, the method comprising the formation of a stack containing: a support substrate formed from a material that is at least partially transparent at a determined wavelength; a layer to be separated; and a separation layer interposed between the support substrate and the layer to be separated, the separation layer being adapted to be separated by exfoliation under the action of radiation having a wavelength corresponding to the determined wavelength. Furthermore, the method comprises, during the step for forming the composite structure, a treatment step modifying the optical properties in reflection at an interface between the support substrate and the separation layer or on an upper face of the support substrate.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: May 9, 2017
    Assignee: SOITEC
    Inventors: Christophe Figuet, Christophe Gourdel
  • Publication number: 20160368259
    Abstract: A process for separating at least two substrates comprising at least two separation interfaces along one of the interfaces includes, before inserting a blade between the substrate, damaging at least one portion of a peripheral region of a chosen one of the interfaces, then inserting the blade and partially parting the substrates, and applying a fluid in a space between the parted substrates while the blade remains inserted therebetween, and decreasing a rupture energy of the chosen interface by stress corrosion involving breaking of siloxane bonds present at the interface.
    Type: Application
    Filed: September 2, 2016
    Publication date: December 22, 2016
    Inventors: Didier Landru, Christophe Figuet
  • Patent number: 9437473
    Abstract: A process for separating at least two substrates comprising at least two separation interfaces along one of the interfaces includes, before inserting a blade between the substrate, damaging at least one portion of a peripheral region of a chosen one of the interfaces, then inserting the blade and partially parting the substrates, and applying a fluid in a space between the parted substrates while the blade remains inserted therebetween, and decreasing a rupture energy of the chosen interface by stress corrosion involving breaking of siloxane bonds present at the interface.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: September 6, 2016
    Assignee: SOITEC
    Inventors: Didier Landru, Christophe Figuet
  • Patent number: 9276070
    Abstract: Methods of forming ternary III-nitride materials include epitaxially growing ternary III-nitride material on a substrate in a chamber. The epitaxial growth includes providing a precursor gas mixture within the chamber that includes a relatively high ratio of a partial pressure of a nitrogen precursor to a partial pressure of one or more Group III precursors in the chamber. Due at least in part to the relatively high ratio, a layer of ternary III-nitride material may be grown to a high final thickness with small V-pit defects therein. Semiconductor structures including such ternary III-nitride material layers are fabricated using such methods.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: March 1, 2016
    Assignee: Soitec
    Inventors: Christophe Figuet, Pierre Tomasini
  • Patent number: 9198294
    Abstract: The invention relates to an electronic device for radiofrequency or power applications, comprising a semiconductor layer supporting electronic components on a support substrate, wherein the support substrate comprises a base layer having a thermal conductivity of at least 30 W/mK and a superficial layer having a thickness of at least 5 ?m, the superficial layer having an electrical resistivity of at least 3000 Ohm·cm and a thermal conductivity of at least 30 W/mK. The invention also relates to two processes for manufacturing such a device.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: November 24, 2015
    Assignee: SOITEC
    Inventors: Didier Landru, Luciana Capello, Eric Desbonnet, Christophe Figuet, Oleg Kononchuk
  • Publication number: 20150221544
    Abstract: A process for separating at least two substrates comprising at least two separation interfaces along one of the interfaces includes, before inserting a blade between the substrate, damaging at least one portion of a peripheral region of a chosen one of the interfaces, then inserting the blade and partially parting the substrates, and applying a fluid in a space between the parted substrates while the blade remains inserted therebetween, and decreasing a rupture energy of the chosen interface by stress corrosion involving breaking of siloxane bonds present at the interface.
    Type: Application
    Filed: September 4, 2013
    Publication date: August 6, 2015
    Inventors: Didier Landru, Christophe Figuet
  • Patent number: 8975165
    Abstract: Embodiments relate to semiconductor structures and methods of forming them. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. An In-III-V semiconductor layer is grown with an Indium concentration above a saturation regime by adjusting growth conditions such as a temperature of a growth surface to create a super-saturation regime wherein the In-III-V semiconductor layer will grow with a diminished density of V-pits relative to the saturation regime.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: March 10, 2015
    Assignee: Soitec
    Inventors: Christophe Figuet, Ed Lindow, Pierre Tomasini
  • Publication number: 20140339681
    Abstract: The invention relates to a method for fabricating a composite structure comprising a layer to be separated by irradiation, the method comprising the formation of a stack containing: a support substrate formed from a material that is at least partially transparent at a determined wavelength; a layer to be separated; and a separation layer interposed between the support substrate and the layer to be separated, the separation layer being adapted to be separated by exfoliation under the action of radiation having a wavelength corresponding to the determined wavelength. Furthermore, the method comprises, during the step for forming the composite step, a treatment step modifying the optical properties in reflection at the interface between the support substrate and the separation layer or on the upper face of the support substrate.
    Type: Application
    Filed: July 18, 2012
    Publication date: November 20, 2014
    Applicant: SOITEC
    Inventors: Christophe Figuet, Christophe Gourdel
  • Publication number: 20140217419
    Abstract: Methods of forming ternary III-nitride materials include epitaxially growing ternary III-nitride material on a substrate in a chamber. The epitaxial growth includes providing a precursor gas mixture within the chamber that includes a relatively high ratio of a partial pressure of a nitrogen precursor to a partial pressure of one or more Group III precursors in the chamber. Due at least in part to the relatively high ratio, a layer of ternary III-nitride material may be grown to a high final thickness with small V-pit defects therein. Semiconductor structures including such ternary III-nitride material layers are fabricated using such methods.
    Type: Application
    Filed: April 10, 2014
    Publication date: August 7, 2014
    Applicant: Soitec
    Inventors: Christophe Figuet, Pierre Tomasini
  • Publication number: 20140183601
    Abstract: A method for transferring a layer of semiconductor by providing a donor substrate that includes a useful layer of a semiconductor material, a confinement structure that includes a confinement layer of a semiconductor material having a chemical composition that is different than that of the useful layer, and two protective layers of semiconductor material that is distinct from the confinement layer with the protective layers being arranged on both sides of the confinement layer; introducing ions into the donor substrate, bonding the donor substrate to a receiver substrate, subjecting the donor and receiver substrates to a heat treatment that provides an increase in temperature during which the confinement layer attracts the ions in order to concentrate them in the confinement layer, and detaching the donor substrate from the receiver substrate by breaking the confinement layer.
    Type: Application
    Filed: June 20, 2012
    Publication date: July 3, 2014
    Applicant: SOITEC
    Inventors: Fabrice Lallement, Christophe Figuet, Daniel Delprat
  • Patent number: 8742428
    Abstract: Methods of forming ternary III-nitride materials include epitaxially growing ternary III-nitride material on a substrate in a chamber. The epitaxial growth includes providing a precursor gas mixture within the chamber that includes a relatively high ratio of a partial pressure of a nitrogen precursor to a partial pressure of one or more Group III precursors in the chamber. Due at least in part to the relatively high ratio, a layer of ternary III-nitride material may be grown to a high final thickness with small V-pit defects therein. Semiconductor structures including such ternary III-nitride material layers are fabricated using such methods.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: June 3, 2014
    Assignee: Soitec
    Inventors: Christophe Figuet, Pierre Tomasini
  • Publication number: 20140027714
    Abstract: A quantum well thermoelectric component for use in a thermoelectric device based on the thermoelectric effect, comprising a stack of layers of two materials respectively made on the basis of silicon and silicon-germanium, the first of the two materials, made on the basis of silicon, defining a barrier semiconductor material and the second of the two materials, made on the basis of silicon-germanium, defining a conducting semiconductor material, the barrier semiconductor material having a band gap higher than the band gap of the conducting semiconductor material, wherein the conducting semiconductor material is an alloy comprising silicon, germanium and at least a lattice-matching element, the lattice-matching element(s) being present in order to control a lattice parameter mismatch between the barrier layer made of the barrier semiconductor material and the conducting layer made of the conducting semiconductor material.
    Type: Application
    Filed: April 4, 2012
    Publication date: January 30, 2014
    Applicant: SOITEC
    Inventors: Daniel Delprat, Christophe Figuet, Oleg Kononchuk