Abstract: The present invention relates to a delay line (D LINE) for delaying an input sig al, said input signal comprising a series of samples (IN TIME, LATE, VOID). The nvention is characterized in that it is intended to delay the input signal by a eries of delays and that the series is divided into a series of delay sub-lines ZONE) each intended to write one sample from the series of samples (IN TIME, EAR Y, LATE, VOID) of said input signal, and in that it comprises control means (RD DD GEN) intended to generate read addresses of the samples in the delay sub-line (ZONE) from the series of samples (IN TIME, EARLY, LATE, VOID) of the input sig al. The read addresses are equal to a difference between a write address of a sa ple in the delay sub-lines (ZONE) of the input signal and said delays expressed n a number of chip periods.