Abstract: A method can be used for programming a group of memory cells of a non-volatile memory device in a programming window that has a duration longer than a programming duration of a memory cell. The programming window is subdivided into a number of time intervals. A programming profile that was determined by simulation while taking into account a reference criterion is retrieved. The programming profile includes, for each time interval, a maximum number of memory cells that can be triggered for programming within each time interval. The memory device is programmed in the programming window, interval-wise, using the programming profile.

Abstract: A method can be used for programming a group of memory cells of a non-volatile memory device in a programming window that has a duration longer than a programming duration of a memory cell. The programming window is subdivided into a number of time intervals. A programming profile that was determined by simulation while taking into account a reference criterion is retrieved. The programming profile includes, for each time interval, a maximum number of memory cells that can be triggered for programming within each time interval. The memory device is programmed in the programming window, interval-wise, using the programming profile.

Abstract: A device includes a matrix of active pixels. Each active pixel includes an OLED and a control circuit configured to refresh the active pixel and including at least one transistor having a first conduction terminal coupled to a supply line and a second conduction terminal coupled to the OLED. Supply circuitry is configured to apply a supply voltage to the supply line of each active pixel during the refreshing of the active pixel and for a time period less than a duration of the refreshing of the active pixel.

Abstract: An integrated device includes a semiconducting substrate having a matrix of active pixels formed therein. Each active pixel includes an OLED diode, a first nMOS transistor having its source coupled to an anode of the OLED diode, and a refresh circuit coupled to a gate of the first nMOS transistor. The first nMOS transistor has its source and its substrate coupled together. The first nMOS transistor is situated in and on a first part of the semiconductor substrate, and the refresh circuit is situated in and on a second part of the semiconductor substrate, with the first part and the second part being electrically insulated from one another.

Abstract: A device includes a matrix of active pixels. Each active pixel includes an OLED and a control circuit configured to refresh the active pixel and including at least one transistor having a first conduction terminal coupled to a supply line and a second conduction terminal coupled to the OLED. Supply circuitry is configured to apply a supply voltage to the supply line of each active pixel during the refreshing of the active pixel and for a time period less than a duration of the refreshing of the active pixel.

Abstract: An integrated device includes a semiconducting substrate having a matrix of active pixels formed therein. Each active pixel includes an OLED diode, a first nMOS transistor having its source coupled to an anode of the OLED diode, and a refresh circuit coupled to a gate of the first nMOS transistor. The first nMOS transistor has its source and its substrate coupled together. The first nMOS transistor is situated in and on a first part of the semiconductor substrate, and the refresh circuit is situated in and on a second part of the semiconductor substrate, with the first part and the second part being electrically insulated from one another.

Abstract: A switch for an analog signal may include a main MOS transistor whose source forms an input terminal of the switch and whose drain forms an output terminal of the switch, a capacitor having a first terminal permanently connected to the source of the main transistor, a circuit for charging the capacitor, and a first auxiliary transistor configured to connect the second terminal of the capacitor to the gate of the main transistor in response to a control signal. The charge circuit may include a resistor permanently connecting the second terminal of the capacitor to a power supply line. The capacitor and the resistor may form a high-pass filter having a cutoff frequency lower than the frequency of the analog signal.

Abstract: An output stage of an integrated class-A amplifier in a technology adapted to a first voltage and intended to be powered by a second voltage greater than the first one, including: one or several transistors of a first channel type between a first terminal of application of the second voltage and an output terminal of the stage; transistors of a second channel type between this output terminal and a second terminal of application of the second voltage, wherein: a first transistor of the second channel type has its gate directly connected to an input terminal of the stage; at least a second and a third transistors of the second channel type are in series between the output terminal and said first transistor, the gate of the second transistor being connected to the midpoint of a resistive dividing bridge between said output terminal and the gate of the third transistor, and the gate of the third transistor being biased to a fixed voltage.

Abstract: An output stage of a class-AB amplifier, including: a first transistor of a first channel type between a first terminal of application of a first voltage and an output terminal of the stage, having its gate connected to a first input terminal of the stage; a first transistor of a second channel type between this output terminal and a second terminal of application of the first voltage, having its gate connected to a second input terminal of the stage; and second and third transistors of the second channel type between the output terminal and the first transistor of the second channel type, the gate of the second transistor being connected to the midpoint of a resistive dividing bridge between said output terminal and the gate of the third transistor of the second channel type, and the gate of the third transistor being biased to a fixed voltage.

Abstract: A switch for an analog signal may include a main MOS transistor whose source forms an input terminal of the switch and whose drain forms an output terminal of the switch, a capacitor having a first terminal permanently connected to the source of the main transistor, a circuit for charging the capacitor, and a first auxiliary transistor configured to connect the second terminal of the capacitor to the gate of the main transistor in response to a control signal. The charge circuit may include a resistor permanently connecting the second terminal of the capacitor to a power supply line. The capacitor and the resistor may form a high-pass filter having a cutoff frequency lower than the frequency of the analog signal.

Abstract: An output stage of a class-AB amplifier, including: a first transistor of a first channel type between a first terminal of application of a first voltage and an output terminal of the stage, having its gate connected to a first input terminal of the stage; a first transistor of a second channel type between this output terminal and a second terminal of application of the first voltage, having its gate connected to a second input terminal of the stage; and second and third transistors of the second channel type between the output terminal and the first transistor of the second channel type, the gate of the second transistor being connected to the midpoint of a resistive dividing bridge between said output terminal and the gate of the third transistor of the second channel type, and the gate of the third transistor being biased to a fixed voltage.

Abstract: An output stage of an integrated class-A amplifier in a technology adapted to a first voltage and intended to be powered by a second voltage greater than the first one, including: one or several transistors of a first channel type between a first terminal of application of the second voltage and an output terminal of the stage; transistors of a second channel type between this output terminal and a second terminal of application of the second voltage, wherein: a first transistor of the second channel type has its gate directly connected to an input terminal of the stage; at least a second and a third transistors of the second channel type are in series between the output terminal and said first transistor, the gate of the second transistor being connected to the midpoint of a resistive dividing bridge between said output terminal and the gate of the third transistor, and the gate of the third transistor being biased to a fixed voltage.

Abstract: An inhibit circuit which produces an inhibit signal when a variation in a power supply potential is detected includes a comparator having a negative input connected to a generator producing a reference potential and a positive input connected to an output of a first image circuit producing a first potential that is an image of the power supply potential. The first image circuit includes a diode and a circuit for the production of a reference current parallel-connected between a common point to which the power supply potential is applied and an output of the first image circuit connected to the positive input of the comparator. The circuit has particular utility in portable integrated circuits with very low consumption when idle such as in mobile telephony.

Abstract: A power amplifier circuit including first and second cascade-assembled operational amplifiers having respective first inputs receiving a reference voltage across a decoupling capacitor, respective outputs of which are connected across a load and are looped back on respective second inputs, the second input of the first amplifier receiving, from a coupling capacitor, an input voltage to be amplified, the amplifier circuit including means for separately charging the coupling and decoupling capacitors, upon circuit power-on, from an off or standby state, and means for inhibiting the amplifiers at least during the separate charging.

Abstract: An inhibit circuit which produces an inhibit signal when a variation in a power supply potential is detected includes a comparator having a negative input connected to a generator producing a reference potential and a positive input connected to an output of a first image circuit producing a first potential that is an image of the power supply potential. The first image circuit includes a diode and a circuit for the production of a reference current parallel-connected between a common point to which the power supply potential is applied and an output of the first image circuit connected to the positive input of the comparator. The circuit has particular utility in portable integrated circuits with very low consumption when idle such as in mobile telephony.

Abstract: A power amplifier circuit including first and second cascade-assembled operational amplifiers having respective first inputs receiving a reference voltage across a decoupling capacitor, respective outputs of which are connected across a load and are looped back on respective second inputs, the second input of the first amplifier receiving, from a coupling capacitor, an input voltage to be amplified, the amplifier circuit including means for separately charging the coupling and decoupling capacitors, upon circuit power-on, from an off or standby state, and means for inhibiting the amplifiers at least during the separate charging.

Abstract: An amplifying circuit receiving an input voltage and a reference voltage equal to a fraction of the circuit supply voltage, the reference voltage provided by a time constant circuit, including a circuit for, upon power-on, inhibiting the amplifying circuit for as long as the difference between the value of the provided reference voltage and the voltage at the output of the time constant circuit is greater than a determined threshold.

Abstract: An amplifying circuit receiving an input voltage and a reference voltage equal to a fraction of the circuit supply voltage, the reference voltage provided by a time constant circuit, including a circuit for, upon power-on, inhibiting the amplifying circuit for as long as the difference between the value of the provided reference voltage and the voltage at the output of the time constant circuit is greater than a determined threshold.

Abstract: A process for forming an electrical resistance in an integrated MOS transistor includes applying a first voltage to the source and gate of the MOS transistor, and applying a second voltage to the drain of the MOS transistor. A prebiasing voltage is applied to the substrate of the MOS transistor to make the base/emitter junction of a parasitic bipolar transistor of the MOS transistor conduct. The first and second voltages are capable of initiating a breakdown of the MOS transistor by an avalanche of the drain/substrate junction, an irreversible breakdown of the drain/substrate junction, and a short circuit between the drain and the source.

Abstract: A process and an integrated circuit are intended for obtaining an adjustable electrical resistance, in which a first voltage is applied to an integrated MOS transistor on its source, its gate and its substrate, and a second voltage is applied on its drain, the first and second voltages being able to initiate a breakdown of the MOS transistor by: avalanche of the drain/substrate junction; biasing of the parasitic bipolar transistor of the MOS transistor; irreversible breakdown of the drain/substrate junction; and shorting between the drain and the source.