Abstract: Method of integrity verification of public and private cryptographic key pairs in the additive group of integers modulo n, with n being the product of two prime numbers p and q, the method including the following steps: of computation (201), on the basis of the number n, of a public exponent e of the public key, and of a private exponent d of the private key, of two candidate factors p? and q? corresponding respectively to the numbers p and q, of verification (206) so as to verify the consistency of the private exponent with respect to the public exponent and to the number n, the verification step involving the candidate factors.

Abstract: Devices and methods for masking and unmasking sensitive data, based on a standard cryptographic algorithm defining a ciphering algorithm, and a deciphering algorithm using more resources than the ciphering algorithm are described. The masking of sensitive data is done by applying the deciphering algorithm to the sensitive data to obtain masked sensitive data. The unmasking of the masked sensitive data is done by applying the ciphering algorithm to the masked sensitive data to obtain sensitive data in plain form.

Abstract: Generation of a message m of order ?(n) for a test of the integrity of the generation of a pair of cryptographic keys within the multiplicative group of integers modulo n=p·q, including: —key pair generation including, to generate p and q: a random selection of candidate integers; and a primality test; —a first search of the multiplicative group of integers modulo p for a generator a; —a second search of the multiplicative group of integers modulo q for a generator b; —a third search for a number y, as message m, verifying: 1???n?1, where ?=a mod p and ?=b mod q, the first or second search being performed during the primality test.

Abstract: A smart card reader capable of transmitting a power signal to a smart card to determine a duration WT called Waiting Time in keeping with the standard ISO 7816 and sending commands to the smart card, the reader comprising a detector for detecting a malfunctioning condition of the smart card and being configured to cut the power signal when the malfunctioning condition is fulfilled. This reader is remarkable in that the malfunctioning condition is different to reaching, by a counter configured to be incremented with the time from the sending of a command to the smart card, of a value corresponding to the duration WT elapsed from the sending of the command or reinitialization of the counter in response to the receipt of a protocol message of the smart card.

Abstract: A method of cryptographic processing of data (X), in particular a method protected against fault injection attacks, and an associated device. The processing includes at least one transformation (100, 1001-1006) of an input data item (s) into a result data item (s?). In this case the method includes a step (E204) of verifying the transformation including the following steps: obtaining (E206) a first data item (DV(s?)) that is compressed by applying a compression operation (110, MDV, ADV) to the result data item (s?); obtaining (E208) a second compressed data item (DV(s)) that is compressed by applying the compression operation (110, MDV, ADV) to the input data item (s); determining (E210) a verification data item (DV(s)?) by applying the transformation (100, 1001-1006) to the second compressed data item (DV(s)) and; comparing (E212) the verification data item and the first compressed data item.

Abstract: Devices for providing protection against intrusion in order to protect at least one electronic component. One example of the device includes an enclosure, surrounding the electronic component, which is proof against a specific type of radiation, and at least one piece of equipment selected from a receiver and a transmitter of radiation of that specific type, which is arranged inside the enclosure and substantially tuned to another piece of equipment that is complementary and disposed outside the enclosure. The device also includes a detection module suitable for detecting an intrusion if at least one receiver receives radiation of that specific type.

Abstract: A method of executing a program by a processor, and an electronic entity including such a processor, the method includes the following steps: a calling program calling a subprogram and passing at least one parameter; the subprogram determining a return status indicator; the subprogram determining a return word by using a predetermined function to combine at least the return status indicator and the parameter; returning to the calling program with the determined return word as a result; and the calling program comparing the return word and a determined word determined by using the predetermined function to combine at least one possible value of the return status indicator and the parameter passed when calling the subprogram.

Abstract: Method for generating a pair of public and private cryptographic keys in the additive group of integers modulo n, where n is the product of two prime numbers p and q, the method including the following steps: calculating a public exponent e for the public key, and calculating a private exponent d for the private key from the public exponent and the public modulus, where d·e=1 mod ?(n), ?(n) being the least common multiple between p-1 and q-1, characterized in that the method furthermore includes a step: of checking to check that ?(n)=0 mod (p-1) and ?(n)=0 mod (q-1).

Abstract: Described are examples of a device for providing protection against intrusion in order to protect at least one electronic component, the device comprising an enclosure surrounding the electronic component and proof against a type of radiation, at least one piece of equipment selected from a receiver and a transmitter of radiation of said type arranged inside the enclosure and substantially tuned to another piece of equipment that is complementary and disposed outside the enclosure, and a detection module suitable for detecting an intrusion if at least one receiver receives radiation of said type.

Abstract: A method of testing security of an electronic device against a combination of a side-channel attack and a fault-injection attack implemented during a method of cryptographic processing that includes: delivering a message signature based on a secret parameter and implementing a recombination of at least two intermediate values according to the Chinese remainder theorem; and verifying the signature on the basis of at least one public exponent. The method of testing includes: transmitting a plurality of messages to be signed by said electronic device; disturbing each message, including modifying the message by inserting an identical error for each message, before executing a step of determining one of the intermediate values; and analyzing physical measurements, obtained during the step of verifying the signature as a function of the message to be signed, the identical error for each message, and an assumption of a value of part of the secret parameter.

Abstract: Method of integrity verification of cryptographic key pairs, the method including an integrity test with: at least one first step implementing one of the private and public keys and an initial test datum, the first step making it possible to generate a first result, at least one second step implementing at least the first result and the key not used during the at least one first step, the second step making it possible to generate a second result, and a comparison of the second result and of the initial test datum, characterized in that the test is re-executed upon each positive comparison, and in that the test is executed at least 2 times.

Abstract: Method of integrity verification of public and private cryptographic key pairs in the additive group of integers modulo n, with n being the product of two prime numbers p and q, the method including the following steps: of computation (201), on the basis of the number n, of a public exponent e of the public key, and of a private exponent d of the private key, of two candidate factors p? and q? corresponding respectively to the numbers p and q, of verification (206) so as to verify the consistency of the private exponent with respect to the public exponent and to the number n, the verification step involving the candidate factors.

Abstract: A hand to mouth bite counting device is provided that may be worn on a hand, wrist or arm of a user to silently and continuously count the number of bites of food taken by the user. The bite counting device may include a sensing device that collects data corresponding to a sensed movement, and a processor that implements an algorithm to process the collected data and determine whether data collected within a given interval of time corresponds to a bite of food taken by the user. The processor derives a set of attributes from the data collected within the given interval of time to define the sensed movement. The device also provides feedback, goal setting functionality, and long-term statistics to serve as a dietary aid.

Abstract: Devices and methods for masking and unmasking sensitive data, based on a standard cryptographic algorithm defining a ciphering algorithm, and a deciphering algorithm using more resources than the ciphering algorithm are described. The masking of sensitive data is done by applying the deciphering algorithm to the sensitive data to obtain masked sensitive data. The unmasking of the masked sensitive data is done by applying the ciphering algorithm to the masked sensitive data to obtain sensitive data in plain form.

Abstract: The invention concerns a secure electronic entity (11) containing a time measuring unit (18) and comprising a unit (21) for certifying an information concerning a date or a time interval, the certifying unit (21) receiving from the time measuring unit (18) data concerning the date or the time interval and producing certification data of the information concerning a date or a time interval addressed to and external entity. The invention is applicable in particular to microcircuit cards.

Abstract: A microcircuit card (200) includes means for detecting an attack on the card, and command means (130) capable of blowing a fuse (250) of the card when an attack is detected.

Abstract: A secure data processing method includes the following steps: padding (E206) a memory area (MAC?) with a pad value (A); writing (E208) a first datum in the memory area (MAC?); in the area, reading (E210) a second datum with at least one part of the first datum as it was written in the memory area (MAC?); and executing an operation (E210) using the second datum.

Abstract: Method for security loading of at least one residual memory space including at least one program, in particular in a smart card, consists in carrying out successive cycles for selecting (E13, E23, E33) at least one type of data from a predetermined authorized data set, wherein said authorized data set excludes at least one type of data corresponding to a determined instruction, and in introducing (E14, E24, E34) the at least one type of data selected from the at least one residual memory space in such a way that at least one part of the residual memory space is loaded.

Abstract: A smart card reader (1) capable of transmitting a power signal to a smart card (2) to determine a duration WT called Waiting Time in keeping with the standard ISO 7816 and sending commands to said smart card (2), the reader (1) comprising a detector for detecting a malfunctioning condition of the smart card (2) and being configured to cut said power signal when the malfunctioning condition is fulfilled. This reader is remarkable in that said malfunctioning condition is different to reaching, by a counter configured to be incremented with the time from the sending of a command to the smart card (2), of a value corresponding to the duration WT elapsed from the sending of the command or reinitialisation of the counter in response to the receipt of a protocol message of the smart card (2).

Abstract: A data processing method, whereby an element is subjected to a first operation with a given operand. The method includes a step of updating by a second operation a first variable (B; a0; S?p, S?q) or a second variable (A; a1; Sp, Sq), depending on whether a corresponding bit of the operand=0 or 1; and a step of testing a relationship between a first value (B; a0; S?) derived from the first variable and a second value (A; a1; S) derived from the second variable. A related device is also disclosed.