Abstract: A flash memory device and system include a boot block voltage pump for providing a word line voltage to the boot block of the flash memory. At least one additional voltage pump is provided to supply a word line voltage to the remaining memory blocks. The memory device can be operated according to a specification where data stored in the boot block can be read as valid data before data stored in other memory blocks can be validly read upon memory activation.

Abstract: A flash memory array arrangement having a plurality of erase blocks which can be separately erased. The erase blocks have separate source lines, the state of which is controlled by a source line decoder. In array read, program and erase operations, the source lines of the deselected erase blocks, the blocks that are not being read, programmed or erased, are set to a high impedance level. If a cell in one of the deselected erase blocks is defective in some respect such that the cell is conducting leakage current, the high impedance source line associated with the cell will reduce the likelihood that the defective cell will prevent proper operation of the selected erase block.

Abstract: Multiple modes of operation in a cross point array. The invention is a cross point array that uses a read voltage across a conductive array line pair during a read mode. The read voltage produces a read current that is indicative of a first program state when the read current is at a first level and indicative of a second program state when the read current is at a second level. The read current is ineffective to produce a change in program state. A first voltage pulse is used during a first write mode if a change from a second program state to a first program state is desired. A second voltage pulse is used during a second write mode if a change from the first program state to the second program state is desired.

Abstract: A re-writable memory with multiple memory layers. Using both terminals of a memory cell in a stacked cross point structure for selection purposes allows multiple layers of conductive lines to be selected as long as there is only one memory cell that has two terminals selected. Sharing logic over multiple layers allows driver sets to be reused.

Abstract: An apparatus and method for compensating for a decreasing internal voltage that is generated from a higher external voltage. In response to the internal voltage decreasing in excess of a voltage margin, the amount by which the higher external voltage is reduced in generating the internal voltage is adjusted to raise the internal voltage.

Abstract: A CMOS imager and non-volatile memory are integrated on a single substrate along with logic and support circuitry for decoding and processing optical information received by the CMOS imager. A protective layer covers the non-volatile memory contained on the substrate for blocking light received by the CMOS imager. The protective layer can be a metal layer used as an interconnect over other areas of the substrate or an opaque layer provided during the fabrication process. Integrating a CMOS imager, non-volatile memory and peripheral circuitry for decoding and processing optical information received by the CMOS imager allows for a single chip image sensing device, such as a digital camera.

Abstract: A re-writable memory that uses resistive memory cell elements with non-linear IV characteristics is disclosed. Non-linearity is important in certain memory arrays to prevent unselected cells from being disturbed and to reduce the required current. Non-linearity refers to the ability of the element to block the majority of current up to a certain level, but then, once that level is reached, the element allows the majority of the current over and above that level to flow.

Abstract: Non-volatile memory cell with a single semiconductor device per memory cell. The present invention generally allows for a plurality of memory cells to be formed on a semiconductor substrate that supports a semiconductor device. A multi-resistive state material layer that changes its resistive state between a low resistive state and a high resistive state upon application of a voltage pulse is formed above the substrate, generally at a very high temperature. While the layers fabricated between the substrate and the multi-resistive state material use materials that can withstand high temperature processing, the layers fabricated above the multi-resistive state material do not need to withstand high temperature processing.

Abstract: A memory system including a non-volatile flash memory and a method for simultaneously selecting a plurality of memory blocks are disclosed. The memory system is organized into multiple main blocks each having multiple smaller blocks, emulating a disk drive. Control lines activate a number of modes. In a first mode, high-order address lines select only one block, while in a second mode, user-specified multiple blocks are selected. Blocks are selected by loading registers with selection bits or by using some of the address lines directly as selection bits. Each bit specifies one of the blocks, and each bit is independent of the others. The memory system also includes a predecoder and a controller which controls the predecoder and the registers so as to select at least two blocks of memory cells. In a third mode, all of the blocks are selected, and in a fourth mode, all blocks are deselected. Selecting multiple blocks allows simultaneous erasing, writing, and reading of multiple bytes stored in the memory.

Abstract: Non-volatile memory cell with a single semiconductor device per memory cell. The present invention generally allows for a plurality of memory cells to be formed on a semiconductor substrate that supports a semiconductor device. A multi-resistive state material layer that changes its resistive state between a low resistive state and a high resistive state upon application of a voltage pulse is formed above the substrate, generally at a very high temperature. While the layers fabricated between the substrate and the multi-resistive state material use materials that can withstand high temperature processing, the layers fabricated above the multi-resistive state material do not need to withstand high temperature processing.

Abstract: A non-volatile memory device has an array of memory cells arranged in rows and columns. The memory cells can be externally accessed for programming, erasing and reading operations. Test rows of memory cells are provided in the array to allow for memory cell disturb conditions. The test rows are not externally accessible for standard program and read operations. The test rows are located near bit line driver circuitry to insure the highest exposure to bit line voltages that may disturb memory cells in the array.

Abstract: Providing a multiplexor outputting a reference voltage on unselected lines. A multiplexor that has at least one selected line and multiple unselected lines will have the unselected lines at a reference voltage. The selected line allows at least a portion of voltage to pass. Two gate circuits are used for each line, one that controls whether voltage (or a portion thereof) will pass, the other that connects the first gate circuit to a reference voltage, such as ground. In some embodiments the second gate circuit is always on, but is relatively small, such that the connection to the reference voltage has a weak effect on the output voltage. In other embodiments, the second gate circuit is only on when its associated first gate circuit is off.

Abstract: Providing a cross point, memory array with memory plugs exhibiting a characteristic hysteresis. The memory plugs exhibit a hysteresis that, in the low resistive state, the first write threshold voltage is the point above which any voltages applied across the memory plug have substantially no effect on the resistive state and below which a voltage pulse will alter the resistance of the memory plug. Similarly, in the high resistive state, the second write threshold voltage is the point below which any voltages applied across the memory plug have substantially no effect on the resistive state and above which a voltage pulse will alter the resistance of the memory plug. The read voltages applied to the memory plug are typically above the first write threshold voltage and lower than the second write threshold voltage.

Abstract: A mode control bit is used to adjust a mode of a memory device. The mode control bit is stored in a non-volatile memory location and selects between a data rate, low power consumption mode and a higher power, fast programming mode. In the low power consumption mode the mode control bit reduces the rate at which data bits are programmed into the memory device.

Abstract: Line drivers that fit within a specified line pitch. One method of placing line drivers completely underneath a cross point array requires splitting the line driver up so that a portion of the line drivers is on a first side of the cross point array and the other portion is on the opposite side. However, using this technique requires that the width of the drivers is no larger than the width of the memory cells that are being driven. This can be accomplished by stacking transistors such that line drivers fit within a specified line pitch, but are as long as is necessary to include all the necessary circuit.

Abstract: Cross point memory array using multiple modes of operation. The invention is a cross point memory array that uses a read mode to determine the resistive state of a memory plug, a first write mode to cause the memory plug to change from a first resistive state to a second resistive state, and a second write mode to cause the memory plug to change from the second resistive state back to the first resistive state.

Abstract: Cross point memory array using distinct voltages. The invention is a cross point memory array that applies a first select voltage on one conductive array line, a second select voltage on a second conductive array line, the two conductive array lines uniquely defining a single memory plug. The magnitude of the select voltages depends upon whether a read operation or a write operation is occurring. Additionally, an unselect voltage is applied to the unselected conductive array lines. The unselect voltage can be applied before, after or during the selection process. The unselect voltage is approximately equal to the average of the first select voltage and the second select voltage.

Abstract: A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element. The multi-resistive state element is sandwiched between the electrodes such that the top face of the bottom electrode is in contact with the multi-resistive state element's bottom face and the bottom face of the top electrode is in contact with the multi-resistive state element's top face. The bottom electrode, the top electrode and the multi-resistive state element all have sides that are adjacent to their faces. Furthermore, the sides are at least partially covered by a sidewall layer.

Abstract: Externally triggered leakage detection and repair in a flash memory device. According to one embodiment of the present invention a method includes operating a flash memory device to store data in a number of flash cells and initiating an operation to detect or repair leaky flash cells in the flash memory device by coupling one or more selected signals to the flash memory device from a source external to the flash memory device. According to another embodiment of the present invention a system includes a flash memory device having a number of flash cells and a number of pins coupled to exchange interface signals, address signals, and data signals. The system also includes a controller coupled to the pins of the flash memory device to exchange the interface signals, address signals, and data signals with the flash memory device.

Abstract: A memory system including a non-volatile flash memory and a method for simultaneously selecting a plurality of memory blocks are disclosed. The memory system is organized into multiple main blocks each having multiple smaller blocks, emulating a disk drive. Control lines activate a number of modes. In a first mode, high-order address lines select only one block, while in a second mode, user-specified multiple blocks are selected. Blocks are selected by loading registers with selection bits or by using some of the address lines directly as selection bits. Each bit specifies one of the blocks, and each bit is independent of the others. The memory system also includes a predecoder and a controller which controls the predecoder and the registers so as to select at least two blocks of memory cells. In a third mode, all of the blocks are selected, and in a fourth mode, all blocks are deselected. Selecting multiple blocks allows simultaneous erasing, writing, and reading of multiple bytes stored in the memory.