Patents by Inventor Christophe J. Layer
Christophe J. Layer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9767073Abstract: An arithmetic operation in a data processing unit, preferably by iterative digit accumulations, is proposed. An approximate result of the arithmetic operation is computed iteratively. Concurrently at least two supplementary values of the approximate result of the arithmetic operation are computed, and the final result selected from one of the values of the approximate result and the at least two supplementary values of the arithmetic operation depending on the results of the last iteration step.Type: GrantFiled: June 8, 2015Date of Patent: September 19, 2017Assignee: International Business Machines CorporationInventors: Klaus M. Kroener, Christophe J. Layer, Silvia M. Mueller, Kerstin Schelm
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Patent number: 9753690Abstract: A tool for supporting vector operations in a scalar data path. The tool determines a location for a split in the scalar mode configuration to enable vector mode operations. The tool determines the number of coarse shift multiplexers in conflict at a bit position receiving data from both the left half and the right half of the vector mode configuration. The tool duplicates a coarse shift multiplexer in conflict at the bit position receiving data from both the left half and the right half of the vector mode configuration. The tool duplicates an intermediate data signal in conflict at a signal position receiving data from both the left half and the right half of the vector mode configuration. The tool receives a control signal to split the scalar mode configuration and shift the leading zeros across the left half and the right half of the vector mode configuration.Type: GrantFiled: May 10, 2016Date of Patent: September 5, 2017Assignee: International Business Machines CorporationInventors: Maarten J. Boersma, Markus Kaltenbach, Christophe J. Layer, Silvia M. Mueller
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Publication number: 20160253152Abstract: A tool for supporting vector operations in a scalar data path. The tool determines a location for a split in the scalar mode configuration to enable vector mode operations. The tool determines the number of coarse shift multiplexers in conflict at a bit position receiving data from both the left half and the right half of the vector mode configuration. The tool duplicates a coarse shift multiplexer in conflict at the bit position receiving data from both the left half and the right half of the vector mode configuration. The tool duplicates an intermediate data signal in conflict at a signal position receiving data from both the left half and the right half of the vector mode configuration. The tool receives a control signal to split the scalar mode configuration and shift the leading zeros across the left half and the right half of the vector mode configuration.Type: ApplicationFiled: May 10, 2016Publication date: September 1, 2016Applicant: International Business Machines CorporationInventors: Maarten J. Boersma, Markus Kaltenbach, Christophe J. Layer, Silvia M. Mueller
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Patent number: 9361267Abstract: A hardware circuit component configured to support vector operations in a scalar data path. The hardware circuit component configured to operate in a vector mode configuration and in a scalar mode configuration. The hardware circuit component configured to split the scalar mode configuration into a left half and a right half of the vector mode configuration. The hardware circuit component configured to perform one or more bit shifts over one or more stages of interconnected multiplexers in the vector mode configuration. The hardware circuit component configured to include duplicated coarse shift multiplexers at bit positions that receive data from both the left half and the right half of the vector mode configuration, resulting in one or more coarse shift multiplexers sharing the bit position.Type: GrantFiled: September 3, 2013Date of Patent: June 7, 2016Assignee: International Business Machines CorporationInventors: Maarten J. Boersma, Markus Kaltenbach, Christophe J. Layer, Silvia M. Mueller
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Patent number: 9361268Abstract: A hardware circuit component configured to support vector operations in a scalar data path. The hardware circuit component configured to operate in a vector mode configuration and in a scalar mode configuration. The hardware circuit component configured to split the scalar mode configuration into a left half and a right half of the vector mode configuration. The hardware circuit component configured to perform one or more bit shifts over one or more stages of interconnected multiplexers in the vector mode configuration. The hardware circuit component configured to include duplicated coarse shift multiplexers at bit positions that receive data from both the left half and the right half of the vector mode configuration, resulting in one or more coarse shift multiplexers sharing the bit position.Type: GrantFiled: January 9, 2014Date of Patent: June 7, 2016Assignee: International Business machines CorporationInventors: Maarten J. Boersma, Markus Kaltenbach, Christophe J. Layer, Silvia M. Mueller
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Patent number: 9348796Abstract: An arithmetic operation in a data processing unit, preferably by iterative digit accumulations, is proposed. An approximate result of the arithmetic operation is computed iteratively. Concurrently at least two supplementary values of the approximate result of the arithmetic operation are computed, and the final result selected from one of the values of the approximate result and the at least two supplementary values of the arithmetic operation depending on the results of the last iteration step.Type: GrantFiled: September 19, 2013Date of Patent: May 24, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Klaus M. Kroener, Christophe J. Layer, Silvia M. Mueller, Kerstin Schelm
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Patent number: 9256397Abstract: A fused multiply-adder is disclosed. The fused multiply-adder includes a Booth encoder, a fraction multiplier, a carry corrector, and an adder. The Booth encoder initially encodes a first operand. The fraction multiplier multiplies the Booth-encoded first operand by a second operand to produce partial products, and then reduces the partial products into a set of redundant sum and carry vectors. The carry corrector then generates a carry correction factor for correcting the carry vectors. The adder adds the redundant sum and carry vectors and the carry correction factor to a third operand to yield a final result.Type: GrantFiled: December 3, 2013Date of Patent: February 9, 2016Assignee: International Business Machines CorporationInventors: Maarten J. Boersma, Klaus M. Kroener, Christophe J. Layer, Silvia M. Mueller
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Publication number: 20150269121Abstract: An arithmetic operation in a data processing unit, preferably by iterative digit accumulations, is proposed. An approximate result of the arithmetic operation is computed iteratively. Concurrently at least two supplementary values of the approximate result of the arithmetic operation are computed, and the final result selected from one of the values of the approximate result and the at least two supplementary values of the arithmetic operation depending on the results of the last iteration step.Type: ApplicationFiled: June 8, 2015Publication date: September 24, 2015Inventors: KLAUS M. KROENER, CHRISTOPHE J. LAYER, SILVIA M. MUELLER, KERSTIN SCHELM
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Patent number: 9128758Abstract: According to one aspect of the present disclosure, a method and technique for encoding densely packed decimals is disclosed. The method includes: executing a floating point instruction configured to perform a floating point operation on decimal data in a binary coded decimal (BCD) format; determining whether a result of the operation includes a rounded mantissa overflow; and responsive to determining that the result of the operation includes a rounded mantissa overflow, compressing a result of the operation from the BCD-formatted decimal data to decimal data in a densely packed decimal (DPD) format by shifting select bit values of the BCD formatted decimal data by one digit to select bit positions in the DPD format.Type: GrantFiled: November 15, 2011Date of Patent: September 8, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael K. Kroener, Christophe J. Layer, Petra Leber, Silvia M. Mueller
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Patent number: 9122517Abstract: A fused multiply-adder is disclosed. The fused multiply-adder includes a Booth encoder, a fraction multiplier, a carry corrector, and an adder. The Booth encoder initially encodes a first operand. The fraction multiplier multiplies the Booth-encoded first operand by a second operand to produce partial products, and then reduces the partial products into a set of redundant sum and carry vectors. The carry corrector then generates a carry correction factor for correcting the carry vectors. The adder adds the redundant sum and carry vectors and the carry correction factor to a third operand to yield a final result.Type: GrantFiled: June 11, 2012Date of Patent: September 1, 2015Assignee: International Business Machines CorporationInventors: Maarten J. Boersma, Klaus Michael Kroener, Christophe J. Layer, Silvia M. Mueller
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Patent number: 8977835Abstract: Techniques for reducing issue-to-issue latency by reversing processing order in half-pumped single instruction multiple data (SIMD) execution units are described. In one embodiment a processor functional unit is provided comprising a frontend unit, and execution core unit, a backend unit, an execution order control signal unit, a first interconnect coupled between and output and an input of the execution core unit and a second interconnect coupled between an output of the backend unit and an input of the frontend unit. In operation, the execution order control signal unit generates a forwarding order control signal based on the parity of an applied clock signal on reception of a first vector instruction. This control signal is in turn used to selectively forward first and second portions of an execution result of the first vector instruction via the interconnects for use in the execution of a dependent second vector instruction.Type: GrantFiled: November 14, 2013Date of Patent: March 10, 2015Assignee: International Business Machines CorporationInventors: Maarten J. Boersma, Markus Kaltenbach, Christophe J. Layer, Jens Leenstra, Silvia M. Mueller
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Publication number: 20150067298Abstract: A hardware circuit component configured to support vector operations in a scalar data path. The hardware circuit component configured to operate in a vector mode configuration and in a scalar mode configuration. The hardware circuit component configured to split the scalar mode configuration into a left half and a right half of the vector mode configuration. The hardware circuit component configured to perform one or more bit shifts over one or more stages of interconnected multiplexers in the vector mode configuration. The hardware circuit component configured to include duplicated coarse shift multiplexers at bit positions that receive data from both the left half and the right half of the vector mode configuration, resulting in one or more coarse shift multiplexers sharing the bit position.Type: ApplicationFiled: September 3, 2013Publication date: March 5, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Maarten J. Boersma, Markus Kaltenbach, Christophe J. Layer, Silvia M. Mueller
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Publication number: 20150067299Abstract: A hardware circuit component configured to support vector operations in a scalar data path. The hardware circuit component configured to operate in a vector mode configuration and in a scalar mode configuration. The hardware circuit component configured to split the scalar mode configuration into a left half and a right half of the vector mode configuration. The hardware circuit component configured to perform one or more bit shifts over one or more stages of interconnected multiplexers in the vector mode configuration. The hardware circuit component configured to include duplicated coarse shift multiplexers at bit positions that receive data from both the left half and the right half of the vector mode configuration, resulting in one or more coarse shift multiplexers sharing the bit position.Type: ApplicationFiled: January 9, 2014Publication date: March 5, 2015Inventors: Maarten J. Boersma, Markus Kaltenbach, Christophe J. Layer, Silvia M. Mueller
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Patent number: 8954485Abstract: Mechanisms for utilizing a reduced lookup table circuit to perform an operation in a data processing device are provided. A first input value is input for selecting a subset of values from the reduced lookup table circuit. The reduced lookup table circuit stores only boundary cell values from a fully filled lookup table corresponding to the reduced lookup table circuit. The subset of values comprises only a subset of boundary cell values corresponding to the first input value. A second value is input and a comparison, by the reduced lookup table circuit, of the second value to each of the boundary cell values in the subset of boundary cell values is performed. The reduced lookup table circuit outputs an output value based on results of the comparison of the second value to each of the boundary cell values in the subset of boundary cell values.Type: GrantFiled: September 10, 2012Date of Patent: February 10, 2015Assignee: International Business Machines CorporationInventors: Steven R. Carlough, Klaus M. Kroener, Christophe J. Layer, Silvia Melitta Mueller, Kerstin Schelm
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Patent number: 8949575Abstract: Techniques for reducing issue-to-issue latency by reversing processing order in half-pumped single instruction multiple data (SIMD) execution units are described. In one embodiment a processor functional unit is provided comprising a frontend unit, and execution core unit, a backend unit, an execution order control signal unit, a first interconnect coupled between and output and an input of the execution core unit and a second interconnect coupled between an output of the backend unit and an input of the frontend unit. In operation, the execution order control signal unit generates a forwarding order control signal based on the parity of an applied clock signal on reception of a first vector instruction. This control signal is in turn used to selectively forward first and second portions of an execution result of the first vector instruction via the interconnects for use in the execution of a dependent second vector instruction.Type: GrantFiled: December 14, 2011Date of Patent: February 3, 2015Assignee: International Business Machines CorporationInventors: Maarten J. Boersma, Markus Kaltenbach, Christophe J. Layer, Jens Leenstra, Silvia M. Mueller
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Patent number: 8914431Abstract: Mechanisms for utilizing a reduced lookup table circuit to perform an operation in a data processing device are provided. A first input value is input for selecting a subset of values from the reduced lookup table circuit. The reduced lookup table circuit stores only boundary cell values from a fully filled lookup table corresponding to the reduced lookup table circuit. The subset of values comprises only a subset of boundary cell values corresponding to the first input value. A second value is input and a comparison, by the reduced lookup table circuit, of the second value to each of the boundary cell values in the subset of boundary cell values is performed. The reduced lookup table circuit outputs an output value based on results of the comparison of the second value to each of the boundary cell values in the subset of boundary cell values.Type: GrantFiled: January 3, 2012Date of Patent: December 16, 2014Assignee: International Business Machines CorporationInventors: Steven R. Carlough, Klaus M. Kroener, Christophe J. Layer, Silvia Melitta Mueller, Kerstin Schelm
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Publication number: 20140101214Abstract: An arithmetic operation in a data processing unit, preferably by iterative digit accumulations, is proposed. An approximate result of the arithmetic operation is computed iteratively. Concurrently at least two supplementary values of the approximate result of the arithmetic operation are computed, and the final result selected from one of the values of the approximate result and the at least two supplementary values of the arithmetic operation depending on the results of the last iteration step.Type: ApplicationFiled: September 19, 2013Publication date: April 10, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: KLAUS M. KROENER, CHRISTOPHE J. LAYER, SILVIA M. MUELLER, KERSTIN SCHELM
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Publication number: 20140095568Abstract: A fused multiply-adder is disclosed. The fused multiply-adder includes a Booth encoder, a fraction multiplier, a carry corrector, and an adder. The Booth encoder initially encodes a first operand. The fraction multiplier multiplies the Booth-encoded first operand by a second operand to produce partial products, and then reduces the partial products into a set of redundant sum and carry vectors. The carry corrector then generates a carry correction factor for correcting the carry vectors. The adder adds the redundant sum and carry vectors and the carry correction factor to a third operand to yield a final result.Type: ApplicationFiled: December 3, 2013Publication date: April 3, 2014Inventors: MAARTEN J. BOERSMA, KLAUS M. KROENER, CHRISTOPHE J. LAYER, SILVIA M. MUELLER
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Publication number: 20140075153Abstract: Techniques for reducing issue-to-issue latency by reversing processing order in half-pumped single instruction multiple data (SIMD) execution units are described. In one embodiment a processor functional unit is provided comprising a frontend unit, and execution core unit, a backend unit, an execution order control signal unit, a first interconnect coupled between and output and an input of the execution core unit and a second interconnect coupled between an output of the backend unit and an input of the frontend unit. In operation, the execution order control signal unit generates a forwarding order control signal based on the parity of an applied clock signal on reception of a first vector instruction. This control signal is in turn used to selectively forward first and second portions of an execution result of the first vector instruction via the interconnects for use in the execution of a dependent second vector instruction.Type: ApplicationFiled: November 14, 2013Publication date: March 13, 2014Applicant: International Business Machines CorporationInventors: Maarten J. Boersma, Markus Kaltenbach, Christophe J. Layer, Jens Leenstra, Silvia M. Mueller
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Publication number: 20130332501Abstract: A fused multiply-adder is disclosed. The fused multiply-adder includes a Booth encoder, a fraction multiplier, a carry corrector, and an adder. The Booth encoder initially encodes a first operand. The fraction multiplier multiplies the Booth-encoded first operand by a second operand to produce partial products, and then reduces the partial products into a set of redundant sum and carry vectors. The carry corrector then generates a carry correction factor for correcting the carry vectors. The adder adds the redundant sum and carry vectors and the carry correction factor to a third operand to yield a final result.Type: ApplicationFiled: June 11, 2012Publication date: December 12, 2013Applicant: IBM CorporationInventors: Maarten J. Boersma, Klaus Michael Kroener, Christophe J. Layer, Silvia M. Mueller