Abstract: The invention relates to a channel equalizing and decoding device consisting of a series of modules, each of which comprises an equalizer (10) and a decoder with weighted output (20). The modules of rank higher than 1 receive (i) a sequence of samples coming from a sensor and delayed by a value equal to the processing time of preceding modules and (ii) the output from the preceding module. Said invention is characterized in that each of the modules comprises means for receiving at least two different sequences of samples and an equalizer that can determine one same equalized sequence of samples using the aforementioned minimum two sequences received as two different non-equalized representations of the sequence of samples to be determined.

Abstract: The invention relates to a device for cancelling inter-symbol interference in a sampled digital signal. The device comprises a first filter, for which the optimum transfer function is identical to that of the transmission channel, and which receives a sequence of samples ({{tilde over (d)}n}n?N) representative of the digital signal sent to the input of the transmission channel, a subtractor circuit to subtract the first filter output ({{tilde over (d)}?n}n?N) from the sequence of input samples ({rn}n?N), a second filter tuned to the transmission channel, with an optimum transfer function H*(f), to which the output ({en}n?N) from the subtractor circuit is input, and an adder circuit designed to add the output from the second filter to the sequence of samples ({{tilde over (d)}n}n?N) representative of the digital signal sent to the input of the transmission channel, and thus generating a sequence of complex symbols ({n}n?N) without any inter-symbol interference.

Abstract: An equalizer device is used for digital communications systems having a plurality of receive channels. The equalizer device in normal operation comprises a transversal filter for each receive channel, an adder for summing the receive channels, and a system downstream from the adder including a phase corrector and a recursive portion including a single recursive filter and decision circuit in its forward branch. The equalizer device including decision-taking circuit for evaluating its performance as a function of the output signal from the equalizer device and for responding to the result of this evaluation by switching from a first structure which corresponds to a normal mode of operation to a second structure which corresponds to a convergence mode of operation, and vice versa.

Abstract: The invention relates to a device for cancelling inter-symbol interference in a sampled digital signal. The device comprises a first filter (1), for which the optimum transfer function is identical to that of the transmission channel, and which receives a sequence of samples ({ {tilde over (d)}n}?N) representative of the digital signal sent to the input of the transmission channel, a subtractor circuit to subtract the first filter output ({{tilde over (d)}?n}n?N) from the sequence of input samples ({rn}n?N), a second filter tuned to the transmission channel, with an optimum transfer function H*(f), to which the output ({en}n?N) from the subtractor circuit is input, and an adder circuit designed to add the output from the second filter to the sequence of samples ({{tilde over (d)}n}n?N) representative of the digital signal sent to the input of the transmission channel, and thus generating a sequence of complex symbols ({n}n?N) without any inter-symbol interference.

Abstract: Equalizing and decoding apparatus including a module which comprises an equalizer and a weighted output decoder, the apparatus being characterized in that it comprises a plurality of modules of said type in series, in which each equalizer has at least one transversal filter for reducing noise power and in which each module of rank greater than 1 also receives a stream of channel samples that has been delayed by a quantity equal to the processing time of the preceding modules.

Abstract: The invention relates to a channel equalising and decoding device consisting of a series of modules, each of which comprises an equaliser (10) and a decoder with weighted output (20). The modules of rank higher than 1 receive (i) a sequence of samples coming from a sensor and delayed by a value equal to the processing time of preceding modules and (ii) the output from the preceding module. Said invention is characterised in that each of the modules comprises means for receiving at least two different sequences of samples and an equaliser that can determine one same equalised sequence of samples using the aforementioned minimum two sequences received as two different non-equalised representations of the sequence of samples to be determined.

Abstract: The equalizer circuit for the receiver of a digital communications system is characterized in that its predictor (11) is purely recursive, its phase equalizer (12) is purely transversal, and the relative positions of those two elements are interchangeable, means for evaluating performance in terms of decision error and for causing the two elements to be interchanged in application of a criterion for evaluating the difficulty of reception, the predictor being upstream and optimized in adaptive and self-learning manner to whiten its own output while the phase equalizer (12) is downstream and optimized in adaptive manner during periods of difficult reception, whereas the predictor (11) is downstream and the phase equalizer (12) is upstream, both being optimized jointly in adaptive manner to minimize decision error between the output (d(n)) of the decision circuit (2) and its input (w(n) or y(n)) during periods of easy reception.