Abstract: The present disclosure relates to a memory device comprising an array of memory cells and an operating circuit for managing the operation of the array, the operating circuit comprising an encoding unit configured to generate a codeword, the codeword comprising payload data stored in a plurality of memory cells of the array, parity data associated with the payload data stored in parity cells of the memory array, wherein a number of parity cells to be used to store the parity data is selectable based on a status of the plurality of memory cells and is related to a selected Error Correction Code (ECC) protection level, and extra payload data stored in unused parity cells, the device further comprising a decoding unit configured to perform an ECC operation on the stored codeword based on the selected ECC protection level.

Abstract: The present disclosure relates to operating an array of memory cells, including storing user data in a plurality of memory cells of the memory array, storing parity data associated with the user data in parity cells of the memory array, in which a number of used parity cells is selected based on a status of the memory cells and is related to a selected Error Correction Code (ECC) correction capability, and performing an ECC operation on the plurality of memory cells, the ECC correction capability being based on the selected number of used parity cells. Related memory devices and systems are also herein disclosed.

Abstract: An electrostatic chuck assembly includes a first puck plate including one or more first functional elements, a second puck plate including one or more second functional elements, and an interface layer at least partially bonding the first puck plate and the second puck plate.

Abstract: The present disclosure relates to a method for operating an array of memory cells, the method comprising storing user data in a plurality of memory cells of the array, storing parity data associated with the user data in a plurality of parity cells of the array, and, based on the stored parity data, selecting an Error Correction Code (ECC) correction capability and/or an ECC granularity according to which an ECC operation is to be performed, wherein the selection of the ECC correction capability and/or the ECC granularity is determined by the steps of updating a first register, said first register comprising values which indicate a required ECC correction capability and/or a required ECC granularity to be applied to the memory cells based on a current status of said memory cells, wherein the values of the first register are updated based on a variation of the current status of the memory cells, and wherein an update of the values of the first register corresponds to a variation of the required ECC correction

Abstract: A method includes performing an atomic layer deposition (ALD) process with respect to a plurality of target elements to coat interiors of the plurality of target elements with a protective coating. Performing the ALD process includes alternating delivery of a first precursor inside the plurality of target elements for a first duration to form an adsorption layer on the interiors of the plurality of target elements, alternating purging of the first precursor from the plurality of target elements for a second duration, and alternating delivery of a second precursor inside the plurality of target elements for a third duration to cause the second precursor to react with the adsorption layer and form a target layer on the interiors of the plurality of target elements.

Abstract: The present disclosure relates to defining a minimum number of parity cells for storing parity data, the minimum number of parity cells corresponding to a minimum Error Correction Code (ECC) correction capability, defining a maximum number of parity cells for storing the parity data, the maximum number of parity cells corresponding to a maximum ECC correction capability, storing payload content in a plurality of memory cells of a memory array, and, based on a current status of the memory cells storing the payload, selecting a number of parity cells to be used for storing the parity data between the minimum number and the maximum number. The payload is stored in at least part of the parity cells which are not selected to store parity data. Related memory devices and systems are also herein disclosed.

Abstract: The present disclosure includes apparatuses, methods, and systems for unbalanced programmed data states in memory. An embodiment includes a memory having a group of memory cells, and circuitry configured to determine a quantity of the memory cells of the group to program to a first data state, wherein the determined quantity of memory cells is less than or greater than half of the memory cells of the group, program the determined quantity of the memory cells of the group to the first data state, and program a remaining quantity of the memory cells of the group to a second data state.

Abstract: The present disclosure relates to a method for operating an array of memory cells, the method comprising storing user data in a plurality of memory cells of the array, storing parity data associated with the user data in a plurality of parity cells of the array, and, based on the stored parity data, selecting an Error Correction Code (ECC) correction capability and/or an ECC granularity according to which an ECC operation is to be performed, wherein the selection of the ECC correction capability and/or the ECC granularity is determined by the steps of updating a first register, said first register comprising values which indicate a required ECC correction capability and/or a required ECC granularity to be applied to the memory cells based on a current status of said memory cells, wherein the values of the first register are updated based on a variation of the current status of the memory cells, and wherein an update of the values of the first register corresponds to a variation of the required ECC correction

Abstract: Embodiments of packaged chamber components and methods of packaging chamber components are provided herein. In some embodiments, a packaged chamber component for use in a process chamber includes: an insert having an annular trench disposed about a raised inner portion, wherein the annular trench is disposed between the raised inner portion and an outer lip, wherein a ledge couples the raised inner portion to the outer lip, wherein the ledge includes a first portion and a second portion disposed radially outward of the first portion, and wherein the second portion includes a resting surface that extends upward and radially outward of an upper surface of the first portion; and a chamber component disposed in the annular trench of the insert and supported by the resting surface such that one or more critical surfaces of the chamber component are spaced apart from the insert.

Abstract: The present disclosure relates to a method comprising the steps of defining a minimum number of parity cells for storing parity data, the minimum number of parity cells corresponding to a minimum Error Correction Code (ECC) correction capability, defining a maximum number of parity cells for storing the parity data, the maximum number of parity cells corresponding to a maximum ECC correction capability, storing payload content in a plurality of memory cells of a memory array, and, based on a current status of the memory cells storing the payload, selecting a number of parity cells to be used for storing the parity data between the minimum number and the maximum number. The payload is stored in at least part of the parity cells which are not selected to store parity data. Related memory devices and systems are also herein disclosed.

Abstract: The present disclosure includes apparatuses, methods, and systems for unbalanced programmed data states in memory. An embodiment includes a memory having a group of memory cells, and circuitry configured to determine a quantity of the memory cells of the group to program to a first data state, wherein the determined quantity of memory cells is less than or greater than half of the memory cells of the group, program the determined quantity of the memory cells of the group to the first data state, and program a remaining quantity of the memory cells of the group to a second data state.

Abstract: Embodiments of the disclosure relate to articles, coated chamber components, and techniques of coating chamber components and systems. In particular, disclosed is a chamber component and methods of forming the chamber component that includes a substrate and a first layer disposed on the substrate, the first layer including a metal with a first atomic concentration. The chamber component further includes a second layer disposed on the first layer, the second layer including the metal with a second atomic concentration that is at least 5 percent higher than the first atomic concentration.

Abstract: A system configured to determine poses of a pair hand-held controller in a physical environment and to utilize the poses as an input to control or manipulate a virtual environment or mixed reality environment. In some cases, the system may capture image data of the controllers having constellations or patterns. The system may analyze the image data to identify points associated with the constellations or patterns and to determine the poses and disambiguate the identity of the individual controllers based on the identified points and a stored model associated with each controller.

Abstract: The present disclosure relates to a memory device comprising an array of memory cells and an operating circuit for managing the operation of the array, the operating circuit comprising an encoding unit configured to generate a codeword, the codeword comprising payload data stored in a plurality of memory cells of the array, parity data associated with the payload data stored in parity cells of the memory array, wherein a number of parity cells to be used to store the parity data is selectable based on a status of the plurality of memory cells and is related to a selected Error Correction Code (ECC) protection level, and extra payload data stored in unused parity cells, the device further comprising a decoding unit configured to perform an ECC operation on the stored codeword based on the selected ECC protection level.

Abstract: The present disclosure relates to a method for operating an array of memory cells, the method comprising the steps of storing user data in a plurality of memory cells of the memory array, storing parity data associated with the user data in a number of parity cells of the memory array, the parity data corresponding to one of a plurality of selectable Error Correction Code (ECC) correction capabilities from a minimum ECC correction capability to a maximum ECC correction capability, calculating an ECC syndrome from the stored user data and parity data, based on the ECC syndrome, determining a number of errors in the data, and, based on the determined number of errors, selecting an ECC correction capability of the plurality of ECC correction capabilities. Related memory devices and systems are also herein disclosed.

Abstract: The present disclosure relates to a method for operating an array of memory cells, the method comprising storing user data in a plurality of memory cells of the array, storing parity data associated with the user data in a plurality of parity cells of the array, and, based on the stored parity data, selecting an Error Correction Code (ECC) correction capability and/or an ECC granularity according to which an ECC operation is to be performed, wherein the selection of the ECC correction capability and/or the ECC granularity is determined by the steps of updating a first register, said first register comprising values which indicate a required ECC correction capability and/or a required ECC granularity to be applied to the memory cells based on a current status of said memory cells, wherein the values of the first register are updated based on a variation of the current status of the memory cells, and wherein an update of the values of the first register corresponds to a variation of the required ECC correction

Abstract: The present disclosure relates to a method comprising the steps of defining a minimum number of parity cells for storing parity data, the minimum number of parity cells corresponding to a minimum Error Correction Code (ECC) correction capability, defining a maximum number of parity cells for storing the parity data, the maximum number of parity cells corresponding to a maximum ECC correction capability, storing payload content in a plurality of memory cells of a memory array, and, based on a current status of the memory cells storing the payload, selecting a number of parity cells to be used for storing the parity data between the minimum number and the maximum number. The payload is stored in at least part of the parity cells which are not selected to store parity data. Related memory devices and systems are also herein disclosed.

Abstract: The present disclosure relates to a method for operating an array of memory cells, the method comprising the steps of storing user data in a plurality of memory cells of the memory array, storing parity data associated with the user data in parity cells of the memory array, wherein a number of used parity cells is selected based on a status of the memory cells and is related to a selected Error Correction Code (ECC) correction capability, and performing an ECC operation on the plurality of memory cells, the ECC correction capability being based on the selected number of used parity cells. Related memory devices and systems are also herein disclosed.

Abstract: Described herein is a protective coating composition that provides erosion and corrosion resistance to a coated article (such as a chamber component) upon the article's exposure to harsh chemical environment (such as hydrogen based and/or halogen based environment) and/or upon the article's exposure to high energy plasma. Also described herein is a method of coating an article with the protective coating using electronic beam ion assisted deposition, physical vapor deposition, or plasma spray. Also described herein is a method of processing wafer, which method exhibits, on average, less than about 5 yttrium based particle defects per wafer.

Abstract: A pre-vaporisation tube for a turbine engine combustion chamber includes a main body ROOM defining a first inner duct configured to have an injector mounted therein. The tube includes a first end attached to a wall of the chamber, and at least two end pieces are arranged at a second end of the body and define second inner ducts. The end pieces include first portions and second portions, respectively. The second portions each include two coaxial cylindrical walls which are inner and outer coaxial cylindrical walls, respectively, and which define an annular cavity therebetween. The inner wall defines an inner passage and has first openings for fluid communication between the passage and the annular cavity.