Abstract: Disclosed are various embodiments of a single ended laser driving circuit. One embodiment includes a thin oxide gate switched by a data signal, the thin oxide gate configured to output a switching signal. The embodiment also includes a thick oxide current source configured to generate a bias current and a modulation current at a laser operating voltage, the modulation current based upon the switching signal, the thick oxide current source further configured to provide the bias current to the laser. The laser is configured to operate at the laser operating voltage based upon the modulation current and the bias current.

Abstract: Various systems and methods are provided to achieve laser power control. In one embodiment, a system is provided that comprises a counter that holds a digital value. An digital-to-analog converter is employed to convert the digital value to an analog current. A data threshold current is generated by a laser driver based upon the analog current. The data threshold current is employed to represent a data value in a data signal employed to drive a laser diode. Also, circuitry is employed to adjust the digital value based upon a comparison between a target threshold current and a feedback current generated from a laser output of the laser diode.

Abstract: Various systems and methods are provided to achieve laser power control. In one embodiment, a system is provided that comprises a counter that holds a digital value. An digital-to-analog converter is employed to convert the digital value to an analog current. A data threshold current is generated by a laser driver based upon the analog current. The data threshold current is employed to represent a data value in a data signal employed to drive a laser diode. Also, circuitry is employed to adjust the digital value based upon a comparison between a target threshold current and a feedback current generated from a laser output of the laser diode.

Abstract: A P-stage shift register or counter is added to the charge pump and/or to the phase frequency detector of a phase locked loop circuit to keep the output clock stable enough from the locked frequency value and available for long enough after the input reference clock has been removed. This mode is called the phase locked loop (PLL) free running mode (FRM) and is activated as soon as the device has detected the loss of the input reference clock of the phase locked loop. Once the free running mode is activated the charge pump automatically enters its high impedance state resulting in a slower frequency shift process at the PLL output in comparison to a conventional PLL. This main advantage of this PLL circuit is that the system clock is kept running for long enough so that the system can issue a fault report through another logic and memory device when the reference clock is suddenly removed either accidentally or not.

Abstract: A P-stage shift register or counter is added to the charge pump and/or to the phase frequency detector of a phase locked loop circuit to keep the output clock stable enough from the locked frequency value and available for long enough after the input reference clock has been removed. This mode is called the phase locked loop (PLL) free running mode (FRM) and is activated as soon as the device has detected the loss of the input reference clock of the phase locked loop. Once the free running mode is activated the charge pump automatically enters its high impedance state resulting in a slower frequency shift process at the PLL output in comparison to a conventional PLL. This main advantage of this PLL circuit is that the system clock is kept running for long enough so that the system can issue a fault report through another logic and memory device when the reference clock is suddenly removed either accidentally or not.

Abstract: A clock recovery circuit comprises first and second voltage-controlled oscillators having identical characteristics. The first oscillator is incorporated into a frequency synthesis loop in such a way as to oscillate, in response to a first control voltage, at a frequency equal to a reference frequency multiplied by a number N. The second voltage-controlled oscillator is incorporated into a phase tracking loop which, when activated, locks its oscillation phase relative to that of the received data signal. The second oscillator delivers the recovered clock signal. A comparator determines whether the frequency of the second oscillator, divided by N, satisfies the condition of not deviating from the reference frequency by more than a predetermined limit value. The phase tracking loop is activated only when the latter condition is satisfied, and the first control voltage is fed to the control input of the second oscillator when the condition is not satisfied.

Abstract: A comparator of phase between a digital signal and a clock signal adapted for the construction of a phase locked loop in integrated circuit form, that includes a first channel formed by a flip-flop and an exclusive OR gate, and a second channel formed by a second exclusive OR gate and a delay circuit whose delay is set to half the period of the clock signal. The first channel receives the digital signal and the clock signal and delivers a first detection signal of transition of the digital signal. The second channel receives only the digital signal and delivers a second detection signal of transition of the digital signal.