Patents by Inventor Christophe Pomarede
Christophe Pomarede has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9873942Abstract: Methods of vapor deposition include multiple vapor sources. A vapor deposition method includes delivering pulses of a vapor containing a first source chemical to a reaction space from at least two separate source vessels simultaneously. The pulses can contain a substantially consistent concentration of the first source chemical. The method can include purging the reaction space of an excess of the first source chemical after the delivering, and delivering pulses of a vapor containing a second source chemical to the reaction space from at least two separate source vessels simultaneously after the purging.Type: GrantFiled: December 11, 2015Date of Patent: January 23, 2018Assignee: ASM IP Holding B.V.Inventors: Christophe Pomarede, Eric Shero, Mohith Verghese, Jan Willem Maes, Chang-Gong Wang
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Publication number: 20160097121Abstract: A vapor deposition method and apparatus including at least two vessels containing a same first source chemical. A controller is programmed to simultaneously pulse to the reaction space doses or pulses of a gas from the vessels, each of the doses having a substantially consistent concentration of the first source chemical. The apparatus may also include at least two vessels containing a same second source chemical. The controller can be programmed to simultaneously pulse to the reaction space doses or pulses of a gas from the vessels containing the second source chemical, each of the doses having a substantially consistent concentration of the second source chemical. The second source chemical can be pulsed to the reaction space after the reaction space is purged of an excess of the first source chemical.Type: ApplicationFiled: December 11, 2015Publication date: April 7, 2016Inventors: Christophe Pomarede, Eric Shero, Mohith Verghese, Jan Willem Maes, Chang-Gong Wang
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Patent number: 9238865Abstract: A vapor deposition method and apparatus including at least two vessels containing a same first source chemical. A controller is programmed to simultaneously pulse to the reaction space doses or pulses of a gas from the vessels, each of the doses having a substantially consistent concentration of the first source chemical. The apparatus may also include at least two vessels containing a same second source chemical. The controller can be programmed to simultaneously pulse to the reaction space doses or pulses of a gas from the vessels containing the second source chemical, each of the doses having a substantially consistent concentration of the second source chemical. The second source chemical can be pulsed to the reaction space after the reaction space is purged of an excess of the first source chemical.Type: GrantFiled: February 6, 2012Date of Patent: January 19, 2016Assignee: ASM IP HOLDING B.V.Inventors: Christophe Pomarede, Eric Shero, Mohith Verghese, Jan Willem Maes, Chang-Gong Wang
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Publication number: 20130203267Abstract: A vapor deposition method and apparatus including at least two vessels containing a same first source chemical. A controller is programmed to simultaneously pulse to the reaction space doses or pulses of a gas from the vessels, each of the doses having a substantially consistent concentration of the first source chemical. The apparatus may also include at least two vessels containing a same second source chemical. The controller can be programmed to simultaneously pulse to the reaction space doses or pulses of a gas from the vessels containing the second source chemical, each of the doses having a substantially consistent concentration of the second source chemical. The second source chemical can be pulsed to the reaction space after the reaction space is purged of an excess of the first source chemical.Type: ApplicationFiled: February 6, 2012Publication date: August 8, 2013Applicant: ASM IP HOLDING B.V.Inventors: Christophe Pomarede, Eric Shero, Mohith Verghese, Jan Willem Maes, Chang-Gong Wang
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Patent number: 7569284Abstract: A high k dielectric film and methods for forming the same are disclosed. The high k material includes two peaks of impurity concentration, particularly nitrogen, such as at a lower interface and upper interface, making the layer particularly suitable for transistor gate dielectric applications. The methods of formation include low temperature processes, particularly CVD using a remote plasma generator and atomic layer deposition using selective incorporation of nitrogen in the cyclic process. Advantageously, nitrogen levels are tailored during the deposition process and temperatures are low enough to avoid interdiffusion and allow maintenance of the desired impurity profile.Type: GrantFiled: July 3, 2008Date of Patent: August 4, 2009Assignee: ASM America, Inc.Inventors: Eric J Shero, Christophe Pomarede
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Publication number: 20080286589Abstract: A high k dielectric film and methods for forming the same are disclosed. The high k material includes two peaks of impurity concentration, particularly nitrogen, such as at a lower interface and upper interface, making the layer particularly suitable for transistor gate dielectric applications. The methods of formation include low temperature processes, particularly CVD using a remote plasma generator and atomic layer deposition using selective incorporation of nitrogen in the cyclic process. Advantageously, nitrogen levels are tailored during the deposition process and temperatures are low enough to avoid interdiffusion and allow maintenance of the desired impurity profile.Type: ApplicationFiled: July 3, 2008Publication date: November 20, 2008Applicant: ASM AMERICA, INC.Inventors: Eric J. Shero, Christophe Pomarede
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Patent number: 7405453Abstract: A high k dielectric film and methods for forming the same are disclosed. The high k material includes two peaks of impurity concentration, particularly nitrogen, such as at a lower interface and upper interface, making the layer particularly suitable for transistor gate dielectric applications. The methods of formation include low temperature processes, particularly CVD using a remote plasma generator and atomic layer deposition using selective incorporation of nitrogen in the cyclic process. Advantageously, nitrogen levels are tailored during the deposition process and temperatures are low enough to avoid interdiffusion and allow maintenance of the desired impurity profile.Type: GrantFiled: May 17, 2005Date of Patent: July 29, 2008Assignee: ASM America, Inc.Inventors: Eric J. Shero, Christophe Pomarede
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Publication number: 20080038936Abstract: Multiple sequential processes are conducted in a reaction chamber to form ultra high quality silicon-containing compound layers, including silicon nitride layers. In a preferred embodiment, a silicon layer is deposited on a substrate using trisilane as the silicon precursor. A silicon nitride layer is then formed by nitriding the silicon layer. By repeating these steps, a silicon nitride layer of a desired thickness is formed.Type: ApplicationFiled: October 23, 2007Publication date: February 14, 2008Applicant: ASM America, Inc.Inventors: Michael Todd, Keith Weeks, Christiaan Werkhoven, Christophe Pomarede
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Publication number: 20080003763Abstract: A method is disclosed for depositing silicon with high deposition rates and good step coverage. The process is performed at high pressures, including close to atmospheric pressures, at temperatures of greater than about 650° C. Silane and hydrogen are flowed over a substrate in a single-wafer chamber. Advantageously, the process maintains good step coverage and high deposition rates (e.g., greater that 50 nn/min) even when dopant gases are added to the process, resulting in commercially practicable rates of deposition for conductive silicon. Despite the high deposition rates, step coverage is sufficient to deposit polysilicon into extremely deep trenches and vias with aspect ratios as high as 40:1, filling such structures without forming voids or keyholes.Type: ApplicationFiled: September 11, 2007Publication date: January 3, 2008Applicant: ASM America, Inc.Inventors: Ivo Raaijmakers, Christophe Pomarede, Cornelius Jeugd, Alexander Gschwandtner, Andreas Grassi
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Publication number: 20060211259Abstract: A method for forming an integrated circuit structure on a semiconductor substrate comprises depositing a high k gate dielectric material over the substrate using an atomic layer deposition process. A silicon oxide capping layer is deposited over the gate dielectric material in a rapid thermal chemical vapor deposition process. A gate electrode is formed over the silicon oxide capping layer.Type: ApplicationFiled: March 21, 2005Publication date: September 21, 2006Inventors: Jan Maes, Hilde Witte, Christophe Pomarede
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Publication number: 20060205230Abstract: Methods are provided herein for treating substrate surfaces in preparation for subsequent nucleation-sensitive depositions (e.g., polysilicon or poly-SiGe) and adsorption-driven deposition (e.g. atomic layer deposition or ALD). Prior to depositing, the surface is treated with non-depositing plasma products. The treated surface more readily nucleates polysilicon and poly-SiGe (such as for a gate electrode), or more readily adsorbs ALD reactants (such as for a gate dielectric). The surface treatment provides surface moieties more readily susceptible to a subsequent deposition reaction, or more readily susceptible to further surface treatment prior to deposition. By changing the surface termination of the substrate with a low temperature radical treatment, subsequent deposition is advantageously facilitated without depositing a layer of any appreciable thickness and without significantly affecting the bulk properties of the underlying material.Type: ApplicationFiled: May 9, 2006Publication date: September 14, 2006Inventors: Christophe Pomarede, Jeff Roberts, Eric Shero
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Publication number: 20060110943Abstract: A nitrogen precursor that has been activated by exposure to a remotely excited species is used as a reactant to form nitrogen-containing layers. The remotely excited species can be, e.g., N2, Ar, and/or He, which has been excited in a microwave radical generator. Downstream of the microwave radical generator and upstream of the substrate, the flow of excited species is mixed with a flow of NH3. The excited species activates the NH3. The substrate is exposed to both the activated NH3 and the excited species. The substrate can also be exposed to a precursor of another species to form a compound layer in a chemical vapor deposition. In addition, already-deposited layers can be nitrided by exposure to the activated NH3 and to the excited species, which results in higher levels of nitrogen incorporation than plasma nitridation using excited N2 alone, or thermal nitridation using NH3 alone, with the same process temperatures and nitridation durations.Type: ApplicationFiled: August 24, 2005Publication date: May 25, 2006Inventors: Johan Swerts, Hilde De Witte, Jan Maes, Christophe Pomarede, Ruben Haverkort, Yuet Wan, Marinus De Blank, Cornelius Van Der Jeugd, Jacobus Beulens
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Publication number: 20060088985Abstract: Sequential processes are conducted in a batch reaction chamber to form ultra high quality silicon-containing compound layers, e.g., silicon nitride layers, at low temperatures. Under reaction rate limited conditions, a silicon layer is deposited on a substrate using trisilane as the silicon precursor. Trisilane flow is interrupted. A silicon nitride layer is then formed by nitriding the silicon layer with nitrogen radicals, such as by pulsing the plasma power (remote or in situ) on after a trisilane step. The nitrogen radical supply is stopped. Optionally non-activated ammonia is also supplied, continuously or intermittently. If desired, the process is repeated for greater thickness, purging the reactor after each trisilane and silicon compounding step to avoid gas phase reactions, with each cycle producing about 5-7 angstroms of silicon nitride.Type: ApplicationFiled: August 25, 2005Publication date: April 27, 2006Inventors: Ruben Haverkort, Yuet Wan, Marinus De Blank, Cornelius van der Jeugd, Jacobus Beulens, Michael Todd, Keith Weeks, Christian Werkhoven, Christophe Pomarede
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Patent number: 7022613Abstract: In accordance with one aspect of the present invention, a method is provided for transporting a workpiece in a semiconductor processing apparatus comprising a transfer chamber, a process chamber, and a gate valve between the transfer chamber and the process chamber. The method comprises vacuum pumping the transfer chamber to achieve a first pressure in the transfer chamber and vacuum pumping the process chamber to achieve a second pressure in the process chamber. An inert gas is flowed into the transfer chamber and shut off in the process chamber. The transfer chamber is isolated from pumping, but pumping continues from the process chamber. The gate valve is opened after isolating the transfer chamber from pumping. The workpiece is then transferred between the transfer chamber and the process chamber. A definitive flow direction from transfer chamber to process chamber is thereby achieved, minimizing risk of back-diffusion.Type: GrantFiled: February 24, 2004Date of Patent: April 4, 2006Assignee: ASM America, Inc.Inventors: Christophe Pomarede, Eric J. Shero, Olli Jylhä
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Patent number: 6960537Abstract: A high k dielectric film and methods for forming the same are disclosed. The high k material includes two peaks of impurity concentration, particularly nitrogen, such as at a lower interface and upper interface, making the layer particularly suitable for transistor gate dielectric applications. The methods of formation include low temperature processes, particularly CVD using a remote plasma generator and atomic layer deposition using selective incorporation of nitrogen in the cyclic process. Advantageously, nitrogen levels are tailored during the deposition process and temperatures are low enough to avoid interdiffusion and allow maintenance of the desired impurity profile.Type: GrantFiled: September 26, 2002Date of Patent: November 1, 2005Assignee: ASM America, Inc.Inventors: Eric J. Shero, Christophe Pomarede
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Publication number: 20050233529Abstract: Methods are provided herein for forming electrode layers over high dielectric constant (“high k”) materials. In the illustrated embodiments, a high k gate dielectric, such as zirconium oxide, is protected from reduction during a subsequent deposition of silicon-containing gate electrode. In particular, a seed deposition phase includes conditions designed for minimizing hydrogen reduction of the gate dielectric, including low hydrogen content, low temperatures and/or low partial pressures of the silicon source gas. Conditions are preferably changed for higher deposition rates and deposition continues in a bulk phase. Desirably, though, hydrogen diffusion is still minimized by controlling the above-noted parameters. In one embodiment, high k dielectric reduction is minimized through omission of a hydrogen carrier gas. In another embodiment, higher order silanes, aid in reducing hydrogen content for a given deposition rate.Type: ApplicationFiled: June 9, 2005Publication date: October 20, 2005Inventors: Christophe Pomarede, Michael Givens, Eric Shero, Michael Todd
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Publication number: 20050212119Abstract: A high k dielectric film and methods for forming the same are disclosed. The high k material includes two peaks of impurity concentration, particularly nitrogen, such as at a lower interface and upper interface, making the layer particularly suitable for transistor gate dielectric applications. The methods of formation include low temperature processes, particularly CVD using a remote plasma generator and atomic layer deposition using selective incorporation of nitrogen in the cyclic process. Advantageously, nitrogen levels are tailored during the deposition process and temperatures are low enough to avoid interdiffusion and allow maintenance of the desired impurity profile.Type: ApplicationFiled: May 17, 2005Publication date: September 29, 2005Inventors: Eric Shero, Christophe Pomarede
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Publication number: 20050118837Abstract: Multiple sequential processes are conducted in a reaction chamber to form ultra high quality silicon-containing compound layers, including silicon nitride layers. In a preferred embodiment, a silicon layer is deposited on a substrate using trisilane as the silicon precursor. A silicon nitride layer is then formed by nitriding the silicon layer. By repeating these steps, a silicon nitride layer of a desired thickness is formed.Type: ApplicationFiled: July 18, 2003Publication date: June 2, 2005Inventors: Michael Todd, Keith Weeks, Christiaan Werkhoven, Christophe Pomarede
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Publication number: 20040255868Abstract: A protective coating is provided herein and methods of using the protective coating for susceptors used in semiconductor deposition chambers are described. In the preferred embodiments, CVD chamber equipment, such as a susceptor, is protected from plasma etch cleaning. Prior to CVD of silicon nitride, the chamber equipment is first coated with an emissivity-stabilizing layer, such as silicon nitride. This layer is then superficially oxidized. After repeated cycles of deposited silicon nitride upon different substrates in sequence, the chamber is emptied of wafers and a plasma cleaning process is conducted. Plasma cleaning is preferably selective against the silicon oxynitride protective coating. After the plasma cleaning process, the emissivity-stabilizing layer is reapplied, oxidized, and a plurality of deposition cycles can commence again.Type: ApplicationFiled: July 6, 2004Publication date: December 23, 2004Inventors: Fred AmRhein, Christophe Pomarede
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Patent number: 6825051Abstract: A protective coating is provided herein and methods of using the protective coating for susceptors used in semiconductor deposition chambers are described. In the preferred embodiments, CVD chamber equipment, such as a susceptor, is protected from plasma etch cleaning. Prior to CVD of silicon nitride, the chamber equipment is first coated with an emissivity-stabilizing layer, such as silicon nitride. This layer is then superficially oxidized. After repeated cycles of deposited silicon nitride upon different substrates in sequence, the chamber is emptied of wafers and a plasma cleaning process is conducted. Plasma cleaning is preferably selective against the silicon oxynitride protective coating. After the plasma cleaning process, the emissivity-stabilizing layer is reapplied, oxidized, and a plurality of deposition cycles can commence again.Type: GrantFiled: May 17, 2002Date of Patent: November 30, 2004Assignee: ASM America, Inc.Inventors: Fred AmRhein, Christophe Pomarede