Patents by Inventor Christophe Regnier

Christophe Regnier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9647724
    Abstract: A wireless unit includes a first motion sensitive device; communications circuitry for wirelessly communicating with a further wireless unit; and a processing device configured to compare at least one first motion vector received from the first motion sensitive device with at least one second motion vector received from a second motion sensitive device of the further wireless unit.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: May 9, 2017
    Assignees: STMicroelectronics SA, STMicroeletronics (Crolles 2) SAS
    Inventors: Pascal Urard, Christophe Regnier, Daniel Gloria, Olivier Hinsinger, Philippe Cavenel, Lionel Balme
  • Patent number: 9006851
    Abstract: A stand-alone device comprising a silicon wafer having its front surface including a first layer of a first conductivity type and a second layer of a second conductivity type forming a photovoltaic cell; first vias crossing the wafer from the rear surface of the first layer and second vias crossing the wafer from the rear surface of the second layer; metallization levels on the rear surface of the wafer, the external level of these metallization levels defining contact pads; an antenna formed in one of the metallization levels; and one or several chips assembled on said pads; the metallization levels being shaped to provide selected interconnects between the different elements of the device.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: April 14, 2015
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Christophe Regnier, Olivier Hinsinger, Daniel Gloria, Pascal Urard
  • Publication number: 20120032291
    Abstract: A stand-alone device comprising a silicon wafer having its front surface including a first layer of a first conductivity type and a second layer of a second conductivity type forming a photovoltaic cell; first vias crossing the wafer from the rear surface of the first layer and second vias crossing the wafer from the rear surface of the second layer; metallization levels on the rear surface of the wafer, the external level of these metallization levels defining contact pads; an antenna formed in one of the metallization levels; and one or several chips assembled on said pads; the metallization levels being shaped to provide selected interconnects between the different elements of the device.
    Type: Application
    Filed: August 4, 2011
    Publication date: February 9, 2012
    Applicants: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Christophe Regnier, Olivier Hinsinger, Daniel Gloria, Pascal Urard
  • Patent number: 7829449
    Abstract: An electronic integrated circuit is fabricated by forming on a substrate, of which a part is composed of absorbing material, a portion made of a sacrificial material. The sacrificial material includes cobalt, nickel, titanium, tantalum, tungsten, molybdenum, gallium, indium, silver, gold, iron and/or chromium. A rigid portion is then formed in fixed contact with the substrate, on one side of the portion of sacrificial material opposite to the part of the substrate composed of absorbing material. The circuit is heated such that the sacrificial material is absorbed into the part of the substrate composed of absorbing material. A substantially empty volume is thus created in place of the portion of sacrificial material. The volume that is substantially empty can replace a dielectric material situated between the electrodes of a capacitor.
    Type: Grant
    Filed: February 10, 2005
    Date of Patent: November 9, 2010
    Assignees: STMicroelectronics (Crolles 2) SAS, Koninklijke Phillips Electronics N.V.
    Inventors: Christophe Regnier, Aurelie Humbert
  • Patent number: 7378692
    Abstract: An integrated electronic circuit with at least at least one passive electronic component and at least one active electronic component. The passive electronic component is formed within an insulating material disposed on a substrate. The active component is formed within a volume of substantially single-crystal semiconductor material disposed on top of the passive component.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: May 27, 2008
    Assignee: STMicroelectronics SA
    Inventors: Philippe Delpech, Christophe Regnier, Sebastien Cremer, Stephane Monfray
  • Publication number: 20070170538
    Abstract: An electronic integrated circuit is fabricated by forming on a substrate, of which a part is composed of absorbing material, a portion made of a sacrificial material. The sacrificial material includes cobalt, nickel, titanium, tantalum, tungsten, molybdenum, gallium, indium, silver, gold, iron and/or chromium. A rigid portion is then formed in fixed contact with the substrate, on one side of the portion of sacrificial material opposite to the part of the substrate composed of absorbing material. The circuit is heated such that the sacrificial material is absorbed into the part of the substrate composed of absorbing material. A substantially empty volume is thus created in place of the portion of sacrificial material. The volume that is substantially empty can replace a dielectric material situated between the electrodes of a capacitor.
    Type: Application
    Filed: February 10, 2005
    Publication date: July 26, 2007
    Inventors: Christophe Regnier, Aurelie Humbert
  • Patent number: 7202137
    Abstract: A process for producing an integrated electronic circuit. The process begins with the production of a first electronic component and a second electronic component that are superposed on top of a substrate. A volume of temporary material is formed on the substrate at the position of the second electronic component. The first electronic component is then produced above the volume of temporary material relative to the substrate, and then the second electronic component is produced using at least one shaft for access to the temporary material. The first electronic component may be an active component and the second electronic component may be a passive component.
    Type: Grant
    Filed: May 20, 2004
    Date of Patent: April 10, 2007
    Assignee: STMicroelectronics SA
    Inventors: Philippe Delpech, Christophe Regnier, Sebastien Cremer, Stephane Monfray
  • Patent number: 7188411
    Abstract: A process for forming portions of a compound material within an electronic circuit includes the formation of a cavity having at least one opening facing onto an access surface. The cavity furthermore has an internal wall with at least one region made of an initial material (for example, silicon). A metal is deposited close to the region of initial material. The circuit is then heated to form a portion of the compound material (for example, a silicide) in the region of initial material inside the cavity. The compound material is formed from elements of the initial material and from some of the metal deposited. The excess metal that has not formed some of the compound material is then removed from the cavity.
    Type: Grant
    Filed: September 8, 2003
    Date of Patent: March 13, 2007
    Assignee: STMicroelectronics S.A.
    Inventors: Philippe Coronel, Christophe Regnier, François Wacquant, Thomas Skotnicki
  • Publication number: 20060189057
    Abstract: An integrated electronic circuit with at least at least one passive electronic component and at least one active electronic component. The passive electronic component is formed within an insulating material disposed on a substrate. The active component is formed within a volume of substantially single-crystal semiconductor material disposed on top of the passive component.
    Type: Application
    Filed: April 27, 2006
    Publication date: August 24, 2006
    Applicant: STMicroelectronics SA
    Inventors: Philippe Delpech, Christophe Regnier, Sebastien Cremer, Stephane Monfray
  • Patent number: 7041585
    Abstract: A process for producing an electronic component includes covering a substrate with a portion defining, with the substrate, a volume at least partly filled with a temporary material. The temporary material is then removed via chimney for access to said volume. A deposition of a fill material is then made in said volume, the fill material being obtained from precursors supplied via the chimney. The process is particularly suitable for producing a gate of an MOS-type transistor. In this case, the fill material is conducting or semiconducting, and an electrically insulating coating material may also be deposited in said volume before the (semi) conducting fill material. The process also includes defining a trench in a substrate filled with a temporary material. The filled trench is then covered with a circuit portion. The temporary material is then removed via a chimney for access to the trench. A deposition of low dielectric fill material is then made in the trench.
    Type: Grant
    Filed: August 7, 2003
    Date of Patent: May 9, 2006
    Assignee: STMicroelectronics S.A.
    Inventors: Jessy Bustos, Philippe Coronel, Christophe Regnier, François Wacquant, Brice Tavel, Thomas Skotnicki
  • Patent number: 7033887
    Abstract: A process for producing an integrated electronic circuit that includes a capacitor comprises the formation of a stack on top of a substrate (100, 101). The stack comprises a first volume of a temporary material, a second volume (2) of at least one insulating dielectric and a third volume (3) of a first electrically conducting material. After a coating material (4) has been deposited on the stack, the temporary material is removed via access shafts (C1, C2) that are formed between a surface (S) of the circuit and the first volume. The temporary material is then replaced with a second, electrically conducting material.
    Type: Grant
    Filed: May 20, 2004
    Date of Patent: April 25, 2006
    Assignee: STMicroelectronics SA
    Inventors: Philippe Delpech, Christophe Regnier, Sebastien Cremer
  • Patent number: 7022595
    Abstract: A method for the selective formation of a suicide on a slice of semiconductor material that comprises exposed regions to be silicided and exposed regions not to be silicided, comprising the following steps: a) forming a resist thin mask on top of the regions not to be silicided; b) implanting ions wafer-scale through said mask so as to form beneath the resist layer an implantation residue layers using the resist layer; c) removing the resist layer; d) depositing conformally a metal layer on the wafer; e) performing rapid heat treatment so as to form a silicide by siliciding the metal deposited at step d); and f) removing the metal that has not reacted to the heat treatment of step e).
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: April 4, 2006
    Assignee: STMicroelectronics SA
    Inventors: Christophe Regnier, François Wacquant
  • Publication number: 20050208765
    Abstract: A process for forming a silicide on top of at least one silicon portion on the surface of a semiconductor wafer, comprising the following steps: a) implanting, at a defined depth in the silicon portion, through a dielectric layer, of ions that have the property of limiting the silicidation of metals; b) performing heat treatment; c) depositing a metal layer, the metal being capable of forming a silicide by thermal reaction with the silicon; d) performing rapid thermal processing suitable for siliciding the metal deposited at step c); and e) removing the metal that has not reacted to the thermal processing of step d). Advantageously, the thickness of the silicide layer created at step d) is controlled by a suitable choice of the depth of the implantation carried out in step a).
    Type: Application
    Filed: June 18, 2004
    Publication date: September 22, 2005
    Applicants: STMicroelectronics, SA, Koninklijke Philips Electronics N.V.
    Inventors: Francois Wacquant, Christophe Regnier, Benoit Froment, Damien Lenoble, Rebha El Farhane
  • Publication number: 20050064638
    Abstract: A method for the selective formation of a suicide on a slice of semiconductor material that comprises exposed regions to be silicided and exposed regions not to be silicided, comprising the following steps: a) forming a resist thin mask on top of the regions not to be silicided; b) implanting ions wafer-scale through said mask so as to form beneath the resist layer an implantation residue layers using the resist layer; c) removing the resist layer; d) depositing conformally a metal layer on the wafer; e) performing rapid heat treatment so as to form a silicide by siliciding the metal deposited at step d); and f) removing the metal that has not reacted to the heat treatment of step e).
    Type: Application
    Filed: June 18, 2004
    Publication date: March 24, 2005
    Applicant: STMicroelectronics, SA
    Inventors: Christophe Regnier, Francois Wacquant
  • Publication number: 20050037593
    Abstract: A process for producing an integrated electronic circuit comprises the production of a first electronic component and a second electronic component that are superposed on top of a substrate. A volume of temporary material is formed on the substrate at the position of the second electronic component. The first electronic component is then produced above the volume of temporary material relative to the substrate, and then the second electronic component is produced using at least one shaft for access to the temporary material. The first electronic component may be an active component and the second electronic component may be a passive component.
    Type: Application
    Filed: May 20, 2004
    Publication date: February 17, 2005
    Applicant: STMICROELECTRONICS SA
    Inventors: Philippe Delpech, Christophe Regnier, Sebastien Cremer, Stephane Monfray
  • Publication number: 20050032303
    Abstract: A process for producing an integrated electronic circuit that includes a capacitor comprises the formation of a stack on top of a substrate (100, 101). The stack comprises a first volume of a temporary material, a second volume (2) of at least one insulating dielectric and a third volume (3) of a first electrically conducting material. After a coating material (4) has been deposited on the stack, the temporary material is removed via access shafts (C1, C2) that are formed between a surface (S) of the circuit and the first volume. The temporary material is then replaced with a second, electrically conducting material.
    Type: Application
    Filed: May 20, 2004
    Publication date: February 10, 2005
    Applicant: STMICROELECTRONICS SA
    Inventors: Philippe Delpech, Christophe Regnier, Sebastien Cremer
  • Publication number: 20040126977
    Abstract: A process for producing an electronic component includes covering a substrate with a portion defining, with the substrate, a volume at least partly filled with a temporary material. The temporary material is then removed via chimney for access to said volume. A deposition of a fill material is then made in said volume, the fill material being obtained from precursors supplied via the chimney. The process is particularly suitable for producing a gate of an MOS-type transistor. In this case, the fill material is conducting or semiconducting, and an electrically insulating coating material may also be deposited in said volume before the (semi)conducting fill material. The process also includes defining a trench in a substrate filled with a temporary material. The filled trench is then covered with a circuit portion. The temporary material is then removed via a chimney for access to the trench. A deposition of low dielectric fill material is then made in the trench.
    Type: Application
    Filed: August 7, 2003
    Publication date: July 1, 2004
    Inventors: Jessy Bustos, Philippe Coronel, Christophe Regnier, Francois Wacquant, Brice Tavel, Thomas Skotnicki
  • Publication number: 20040124468
    Abstract: A process for forming portions of a compound material within an electronic circuit includes the formation of a cavity having at least one opening facing onto an access surface. The cavity furthermore has an internal wall with at least one region made of an initial material (for example, silicon). A metal is deposited close to the region of initial material. The circuit is then heated to form a portion of the compound material (for example, a silicide) in the region of initial material inside the cavity. The compound material is formed from elements of the initial material and from some of the metal deposited. The excess metal that has not formed some of the compound material is then removed from the cavity.
    Type: Application
    Filed: September 8, 2003
    Publication date: July 1, 2004
    Inventors: Philippe Coronel, Christophe Regnier, Francois Wacquant, Thomas Skotnicki