Abstract: Devices and techniques for parking threads in a barrel processor for managing cache eviction requests are described herein. A barrel processor includes eviction circuitry and is configured to perform operations to: (a) detect a thread that includes a memory access operation, the thread entering a memory request pipeline of the barrel processor; (b) determine that a data cache line has to be evicted from a data cache for the thread to perform the memory access operation; (c) copy the thread into a park queue; (d) evict a data cache line from the data cache; (e) identify an empty cycle in the memory request pipeline; (f) schedule the thread to execute during the empty cycle; and (g) remove the thread from the park queue.

Abstract: Devices and techniques for parking threads in a barrel processor for managing hazard clearing are described herein. A barrel processor includes hazard management circuitry that is used to receive an indication of an instruction executing in a compute pipeline of the barrel processor, the instruction having encountered a hazard and unable to progress through the compute pipeline; store the indication of the instruction in a hazard memory; receive a signal indicating that the hazard has cleared; and cause the instruction to be rescheduled at the beginning of the compute pipeline in response to the signal.

Abstract: Devices and techniques for parking threads in a barrel processor for managing cache eviction requests are described herein. A barrel processor includes eviction circuitry and is configured to perform operations to: (a) detect a thread that includes a memory access operation, the thread entering a memory request pipeline of the barrel processor; (b) determine that a data cache line has to be evicted from a data cache for the thread to perform the memory access operation; (c) copy the thread into a park queue; (d) evict a data cache line from the data cache; (e) identify an empty cycle in the memory request pipeline; (f) schedule the thread to execute during the empty cycle; and (g) remove the thread from the park queue.

Abstract: Devices and techniques for asynchronous event message handing in a processor are described herein. A barrel multithreaded processor may include an asynchronous event handler to receive an indication of a thread create instruction from a parent thread, determine a return value size of return values from the indication of the thread create instruction, determine whether sufficient space exists in the memory to store the return values, allocate space in the memory to store the return parameters in response to determining that there is sufficient space in the memory to store the return values, and provide access to the return values from the allocated space to the parent thread based at least in part on a thread return instruction from the child thread.

Abstract: Various examples are directed to systems and methods for executing a transaction between hardware compute elements of a computing system. A first hardware compute element may send a first write request to a second hardware compute element via a network structure. The first write request may comprise first source identifier data describing the first hardware compute element and first payload data describing a processing task requested by the first hardware compute element. The network structure may store first write request state data describing the first write request. Before the processing task is completed, the second hardware compute element may send a first write confirm message.

Abstract: Various examples are directed to systems and methods for requesting an atomic operation. A first hardware compute element may send a first request via a network structure, where the first request comprises an atomic opcode indicating an atomic operation to be performed by a second hardware compute element. The network structure may provide an address bus from the first hardware compute element for providing the atomic opcode to the second hardware compute element. The second hardware compute element may execute the atomic operation and send confirmation data indicating completion of the atomic operation. The network structure may provide a second bus from the second hardware compute element and the first hardware compute element. The second bus may be for providing the confirmation data from the second hardware compute element to the first hardware compute element.

Abstract: Various examples are directed to an arrangement comprising a first hardware compute element and a hardware balancer element. The first hardware compute element may send a first request message to a hardware balancer element. The first request message may describe a processing task. The hardware balancer element may send a second request message towards a second hardware compute element for executing the processing task and send to the first compute element a first reply message in reply to the first request message. After sending the first reply message, the hardware balancer element may receive a first completion request message indicating that the processing task is assigned and send, to the first hardware computing element, a second completion request message, the second completion request message indicating that the processing task is assigned.

Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums which utilize a pool method whereby a host process executing on the host processor reserves one or more pools of memory for worker threads of the host process. Upon creation of a new thread corresponding to the host process, the worker processor executing the new thread may assign a portion of the previously reserved pool to the new thread. By giving some control to a worker processor to assign memory from a previously reserved pool, threads may be assigned memory resources without additional message overhead from the host processor to the worker processor while at the same time retaining overall memory control with the host processor.

Abstract: Methods, systems, and devices for bias control for a memory device are described. A memory system may store indication of whether data is coherent. In some examples, the indication may be stored as metadata, where a first value indicates that the data is not coherent and a second value or a third value indicate that the data is coherent. When a processing unit or other component of the memory system processes a command to access data, the memory system may operate according to a device bias mode when the indication is the first value, and according to a host bias mode when the indication is the second value or the third value.

Abstract: Devices and techniques for short-thread rescheduling in a processor are described herein. When an instruction for a thread completes, a result is produced. The condition that the same thread is scheduled in a next execution slot and that the next instruction of the thread will use the result can be detected. In response to this condition, the result can be provided directly to an execution unit for the next instruction.

Abstract: Devices and techniques for thread-based processor halting are described herein. A processor monitors control-status register (CSR) values that correspond to a halt condition for a thread. The processor then compares the halt condition to a current state of the thread and halts in response to the current state of the thread meeting the halt condition.

Abstract: Methods, systems, and devices for bias control for a memory device are described. A memory system may store indication of whether data is coherent. In some examples, the indication may be stored as metadata, where a first value indicates that the data is not coherent and a second value or a third value indicate that the data is coherent. When a processing unit or other component of the memory system processes a command to access data, the memory system may operate according to a device bias mode when the indication is the first value, and according to a host bias mode when the indication is the second value or the third value.

Abstract: Methods, systems, and devices for bias control for a memory device are described. A memory system may store indication of whether data is coherent. In some examples, the indication may be stored as metadata, where a first value indicates that the data is not coherent and a second value or a third value indicate that the data is coherent. When a processing unit or other component of the memory system processes a command to access data, the memory system may operate according to a device bias mode when the indication is the first value, and according to a host bias mode when the indication is the second value or the third value.

Abstract: Methods, systems, and devices for bias control for a memory device are described. A memory system may store indication of whether data is coherent. In some examples, the indication may be stored as metadata, where a first value indicates that the data is not coherent and a second value or a third value indicate that the data is coherent. When a processing unit or other component of the memory system processes a command to access data, the memory system may operate according to a device bias mode when the indication is the first value, and according to a host bias mode when the indication is the second value or the third value.