Patents by Inventor Christopher A. Bower
Christopher A. Bower has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150207012Abstract: Multi-junction photovoltaic devices and methods for making multi-junction photovoltaic devices are disclosed. The multi-junction photovoltaic devices comprise a first photovoltaic p-n junction structure having a first interface surface, a second photovoltaic p-n junction structure having a second interface surface, and an optional interface layer provided between the first interface surface and the second interface surface, where the photovoltaic p-n junction structures and optional layers are provided in a stacked multilayer geometry. In an embodiment, the optional interface layer comprises a chalcogenide dielectric layer.Type: ApplicationFiled: January 16, 2015Publication date: July 23, 2015Inventors: John A. ROGERS, Xing SHENG, Christopher A. BOWER, Matthew MEITL, Scott BURROUGHS
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Patent number: 8975753Abstract: A three-dimensional interconnect includes a first substrate bonded to a second substrate, the first substrate including a device layer and a bulk semiconductor layer, a metal pad disposed on the second substrate, an electrically insulating layer disposed between the first and second substrates. The structure has a via-hole extending through the device layer, the bulk semiconductor layer and the electrically insulating layer to the metal pad on the second substrate. The structure has a dielectric coating on a sidewall of the via-hole, and a plasma-treated region of the metal pad disposed on the second substrate. The structure includes a via metal monolithically extending from the plasma-treated region of the metal pad through the via-hole and electrically interconnecting the device layer of the first substrate to the metal pad of the second substrate.Type: GrantFiled: March 3, 2010Date of Patent: March 10, 2015Assignee: Research Triangle InstituteInventors: Charles Kenneth Williams, Christopher A. Bower, Dean Michael Malta, Dorota Temple
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Patent number: 8866081Abstract: A detector array and method for making the detector array. The detector array includes a substrate including a plurality of trenches formed therein, and a plurality of collectors electrically isolated from each other, formed on the walls of the trenches, and configured to collect charged particles incident on respective ones of the collectors and to output from the collectors signals indicative of charged particle collection. In the detector array, adjacent ones of the plurality of trenches are disposed in a staggered configuration relative to one another. The method forms in a substrate a plurality of trenches across a surface of the substrate such that adjacent ones of the trenches are in a staggered sequence relative to one another, forms in the plurality of trenches a plurality of collectors, and connects a plurality of electrodes respectively to the collectors.Type: GrantFiled: February 24, 2009Date of Patent: October 21, 2014Assignee: Research Triangle InstituteInventors: Christopher A. Bower, Kristin Hedgepath Gilchrist, Brian R. Stoner
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Patent number: 8866080Abstract: A detector array and method for making the detector array. The array includes a substrate including a plurality of trenches formed therein, and includes a plurality of collectors electrically isolated from each other, formed on the walls of the trenches, and configured to collect charge particles incident on respective ones of the collectors and to output from said collectors signals indicative of charged particle collection. The array includes a plurality of readout circuits disposed on a side of the substrate opposite openings to the collectors. The readout circuits are configured to read charge collection signals from respective ones of the plurality of collectors.Type: GrantFiled: February 27, 2009Date of Patent: October 21, 2014Assignee: Research Triangle InstituteInventors: Christopher A. Bower, Kristin Hedgepath Gilchrist, Brian R. Stoner, Dorota Temple
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Patent number: 8486765Abstract: A method for making a structure for thermal management of circuit devices. The method provides a first substrate and a second substrate where at least one of the first and second substrates includes a circuit element. The method forms in at least one of the first substrate and the second substrate an entrance through-hole extending through a thickness of the first substrate or the second substrate, forms in at least one of the first substrate and the second substrate an exit through-hole extending through a thickness of the first substrate or the second substrate, forms respective bonding elements on at least one of the first and second substrates, and bonds the first and second substrates at the respective bonding elements to form a seal between the first and second substrates and to form a first coolant channel in between the first and second substrates.Type: GrantFiled: September 21, 2011Date of Patent: July 16, 2013Assignee: Research Triangle InstituteInventors: Philip Garrou, Charles Kenneth Williams, Christopher A. Bower
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Publication number: 20120048596Abstract: A method for making a structure for thermal management of circuit devices. The method provides a first substrate and a second substrate where at least one of the first and second substrates includes a circuit element. The method forms in at least one of the first substrate and the second substrate an entrance through-hole extending through a thickness of the first substrate or the second substrate, forms in at least one of the first substrate and the second substrate an exit through-hole extending through a thickness of the first substrate or the second substrate, forms respective bonding elements on at least one of the first and second substrates, and bonds the first and second substrates at the respective bonding elements to form a seal between the first and second substrates and to form a first coolant channel in between the first and second substrates.Type: ApplicationFiled: September 21, 2011Publication date: March 1, 2012Applicant: Research Triangle InstituteInventors: Philip GARROU, Charles Kenneth Williams, Christopher A. Bower
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Publication number: 20110298134Abstract: A three-dimensional interconnect includes a first substrate bonded to a second substrate, the first substrate including a device layer and a bulk semiconductor layer, a metal pad disposed on the second substrate, an electrically insulating layer disposed between the first and second substrates. The structure has a via-hole extending through the device layer, the bulk semi-conductor layer and the electrically insulating layer to the metal pad on the second substrate. The structure has a dielectric coating on a sidewall of the via-hole, and a plasma-treated region of the metal pad disposed on the second substrate. The structure includes a via metal monolithically extending from the plasma-treated region of the metal pad through the via-hole and electrically interconnecting the device layer of the first substrate to the metal pad of the second substrate.Type: ApplicationFiled: March 3, 2010Publication date: December 8, 2011Applicant: Research Triangle InstituteInventors: Charles Kenneth Williams, Christopher A. Bower, Dean Michael Malta, Dorota Temple
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Patent number: 8035223Abstract: A structure and method for thermal management of integrated circuits. The structure for thermal management of integrated circuits includes first and second substrates bonded together, at least one of the first and second substrates including at least one circuit element, an entrance through-hole having a length extending through a thickness of at least one of the first substrate and the second substrate, an exit through-hole having a length extending through a thickness of at least one of the first substrate and the second substrate, a bonding element forming a seal between the first and second substrates and forming a space between the first and second substrate, and a coolant channel formed in the space between the first and second substrates such that a fluid entering the entrance through-hole transits the coolant channel and the exit through-hole to provide cooling to the circuit element.Type: GrantFiled: August 28, 2007Date of Patent: October 11, 2011Assignee: Research Triangle InstituteInventors: Philip Garrou, Charles Kenneth Williams, Christopher A. Bower
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Publication number: 20110031388Abstract: A detector array and method for making the detector array. The array includes a substrate including a plurality of trenches formed therein, and includes a plurality of collectors electrically isolated from each other, formed on the walls of the trenches, and configured to collect charge particles incident on respective ones of the collectors and to output from said collectors signals indicative of charged particle collection. The array includes a plurality of readout circuits disposed on a side of the substrate opposite openings to the collectors. The readout circuits are configured to read charge collection signals from respective ones of the plurality of collectors.Type: ApplicationFiled: February 27, 2009Publication date: February 10, 2011Applicant: Research Triangle InstituteInventors: Christopher A. Bower, Kristin Hedgepath Gilchrist, Brian R. Stoner, Dorota Temple
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Publication number: 20110017703Abstract: A method and system for treating a surface structure of a workpiece. The method provides a carrier-gel to the surface structure of the workpiece. The carrier-gel includes an etchant for selectively etching a first material of the surface structure and has a gel particle size larger than the surface structure. The method etches the first material from the surface structure by a reaction of the etchant included in the carrier-gel with the first material of the surface structure in order to remove a part of the first material from the surface structure for subsequent device fabrication. The system includes a chemical reactor supporting the workpiece. The chemical reactor is configured to flow the carrier-gel noted to the surface structure of the workpiece in order to remove the first material from the surface structure.Type: ApplicationFiled: February 13, 2009Publication date: January 27, 2011Applicant: Research Triangle InstituteInventors: Dorota Temple, Dean Michael Malta, Christopher A. Bower
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Publication number: 20110006204Abstract: A detector array and method for making the detector array. The detector array includes a substrate including a plurality of trenches formed therein, and a plurality of collectors electrically isolated from each other, formed on the walls of the trenches, and configured to collect charged particles incident on respective ones of the collectors and to output from the collectors signals indicative of charged particle collection. In the detector array, adjacent ones of the plurality of trenches are disposed in a staggered configuration relative to one another. The method forms in a substrate a plurality of trenches across a surface of the substrate such that adjacent ones of the trenches are in a staggered sequence relative to one another, forms in the plurality of trenches a plurality of collectors, and connects a plurality of electrodes respectively to the collectors.Type: ApplicationFiled: February 24, 2009Publication date: January 13, 2011Applicant: RESEARCH TRIANGLE INSTITUTEInventors: Christopher A. Bower, Kristin Hedgepath Gilchrist, Brian R. Stoner
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Publication number: 20090057879Abstract: A structure and method for thermal management of integrated circuits. The structure for thermal management of integrated circuits includes first and second substrates bonded together, at least one of the first and second substrates including at least one circuit element, an entrance through-hole having a length extending through a thickness of at least one of the first substrate and the second substrate, an exit through-hole having a length extending through a thickness of at least one of the first substrate and the second substrate, a bonding element forming a seal between the first and second substrates and forming a space between the first and second substrate, and a coolant channel formed in the space between the first and second substrates such that a fluid entering the entrance through-hole transits the coolant channel and the exit through-hole to provide cooling to the circuit element.Type: ApplicationFiled: August 28, 2007Publication date: March 5, 2009Applicant: Reseach Triangle InstituteInventors: Philip GARROU, Charles Kenneth WILLIAMS, Christopher A. BOWER
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Publication number: 20030207765Abstract: It was discovered that metals useful for cuprate superconductor wires and ribbons, such as Ag, Cu, and Au, are not necessarily desirable for magnesium boride superconductor bodies, since such elements tend to react with Mg and thereby deteriorate the properties of the superconducting MgB2. The invention relates to techniques and materials that provide useful MgB2 superconducting bodies. The invention relates to a method for forming a MgB2 superconducting body, involving providing an intermediate body of a metal cladding; superconducting material or precursor material for superconducting material; and, optionally, a diffusion barrier (depending on the type of metal cladding); performing a cross-section reducing operation on the intermediate body, to provide an elongate body; and performing a heat treatment of the elongate body, to obtain desired properties from the superconducting material (and to also form the superconducting MgB2 material when precursor material is used).Type: ApplicationFiled: August 2, 2001Publication date: November 6, 2003Inventors: Christopher A. Bower, Sungho Jin, Hareesh Mavoori, Robert Bruce Van Dover
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Publication number: 20030133637Abstract: An electrooptic device and method for making the same, including one or more of substrate, a buffer layer, a charge dissipation layer, and electrodes. An F− containing active trapping layer is deposited at the substrate/buffer interface, within the buffer layer, and/or on top of the buffer layer. The active F− ions in the F− containing active trapping layer react with positive ions, such as Li+ from the substrate to form stable compounds such as LiF. Porous material such as carbon nanotubes may be used in place of or in addition to the F− containing active trapping layer. The reduced number of Li+ ions reduces the DC drift of the associated electrooptic device. The profile of the implanted ions may be adjusted to control and/or optimize the properties of the electrooptic device. Fluorine is particularly advantageous because it also lowers the dielectric constant thereby facilitating higher frequency operation.Type: ApplicationFiled: January 16, 2002Publication date: July 17, 2003Inventors: Zhenan Bao, Christopher A. Bower, Sungho Jin, Kevin Cyrus Robinson, Yiu-Man Wong, Wei Zhu
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Publication number: 20030133638Abstract: An electrooptic device and method for making the same, including one or more of substrate, a buffer layer, a charge dissipation layer, and electrodes are disclosed. Active ions, such as F− ions, are implanted the buffer layer. The active ions react with positive ions, such as Li+ from the substrate to form stable compounds such as LiF. The reduced number of mobile Li+ ions reduces the DC drift of the associated electrooptic device. The profile of the implanted ions may be adjusted to control and/or optimize the properties of the electrooptic device. Fluorine is particularly advantageous because it also lowers the dielectric constant, thereby facilitating higher frequency operation.Type: ApplicationFiled: January 16, 2002Publication date: July 17, 2003Inventors: Sungho Jin, Yiu-Man Wong, Wei Zhu, Christopher A. Bower
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Publication number: 20020114949Abstract: The invention provides a process capable of providing elongated nanostructures conformably aligned perpendicular to the local surface, while also allowing control over the diameter, length, and location. The process also permits controllably introducing defects at desired locations along the length. Conformably aligned straight sections are grown under the influence of an electrical field and curly defect regions are grown after switching off the field. A preferred embodiment uses high frequency plasma enhanced chemical vapor deposition (PECVD), typically with microwave-ignited plasma. The extraordinarily high extent of conformal alignment—on both flat and non-flat surfaces—appears to be due to the electrical self-bias imposed on the substrate by the plasma, the field line of which is perpendicular to the substrate surface.Type: ApplicationFiled: February 12, 2002Publication date: August 22, 2002Inventors: Christopher A. Bower, Sungho Jin, Wei Zhu