Abstract: Methods for using predictive shimming to optimize part-to-part alignment. In accordance with one embodiment, the process uses measurement data acquired from mating surfaces and key features to virtually align two parts in a manner that optimizes the final orientation of the parts and determines the geometry of the shim needed to achieve this orientation during assembly.

Abstract: A system for inhibiting operation of a vehicle-based device while the vehicle is in motion includes a motion sensor, a timer, and a time delay override switch in communication with a control circuit. The control circuit selectively outputs one or more enable and/or inhibit signals based on the states of the motion sensor and timer. The time delay override switch can be actuated to place the timer into a timed out state from a timing state.

Abstract: A method of operating a central cache controller (“CCC”) in a first cell of a multiprocessor system comprising multiple cells each including globally shared memory (“GSM”), wherein the first cell is disposed in a first partition and the CCC is connected to a plurality of CPUs of the first cell. In one embodiment, the method comprises, responsive to a new transaction request from one of the CPUs, logging the transaction in a transaction table; determining whether an identity marker in a timeout map corresponding to a cell to which the transaction was issued is set; and, responsive to the corresponding identity marker in the timeout map being set, immediately returning a special error to the one of the CPUs that requested the transaction.

Abstract: A fuel injector nozzle assembly is disclosed. The assembly may include a nozzle casing, a first tip member, and a second tip member. The first tip member may extend longitudinally within the nozzle casing and may define first and second shoulders on the first tip member. The second tip member may extend longitudinally within the nozzle casing and may be arranged in predetermined rotational alignment with the first tip member. The second tip member may define a third shoulder on the second tip member configured to interact with the first shoulder to oppose rotation of the first tip member relative the second tip member in a first direction about a longitudinal axis of the first tip member. The second tip member may further define a fourth shoulder on the second tip member configured to interact with the second shoulder to oppose rotation of the first tip member relative the second tip member in a second direction about a longitudinal axis of the first tip member.

Abstract: A system and method are disclosed for achieving cache coherency in a multiprocessor computer system having a plurality of sockets with processing devices and memory controllers and a plurality of memory blocks. In at least some embodiments, the system includes a plurality of node controllers capable of being respectively coupled to the respective sockets of the multiprocessor computer, a plurality of caching devices respectively coupled to the respective node controllers, and a fabric coupling the respective node controllers, by which cache line request signals can be communicated between the respective node controllers. Cache coherency is achieved notwithstanding the cache line request signals communicated between the respective node controllers due at least in part to communications between the node controllers and the respective caching devices to which the node controllers are coupled.

Abstract: A fuel injector nozzle assembly is disclosed. The assembly may include a nozzle casing, a first tip member, and a second tip member. The first tip member may extend longitudinally within the nozzle casing and may define first and second shoulders on the first tip member. The second tip member may extend longitudinally within the nozzle casing and may be arranged in predetermined rotational alignment with the first tip member. The second tip member may define a third shoulder on the second tip member configured to interact with the first shoulder to oppose rotation of the first tip member relative the second tip member in a first direction about a longitudinal axis of the first tip member. The second tip member may further define a fourth shoulder on the second tip member configured to interact with the second shoulder to oppose rotation of the first tip member relative the second tip member in a second direction about a longitudinal axis of the first tip member.

Abstract: A method of operating a central cache controller (“CCC”) in a first cell of a multiprocessor system comprising multiple cells each including globally shared memory (“GSM”), wherein the first cell is disposed in a first partition and the CCC is connected to a plurality of CPUs of the first cell. In one embodiment, the method comprises, responsive to a new transaction request from one of the CPUs, logging the transaction in a transaction table; determining whether an identity marker in a timeout map corresponding to a cell to which the transaction was issued is set; and, responsive to the corresponding identity marker in the timeout map being set, immediately returning a special error to the one of the CPUs that requested the transaction.

Abstract: A clock synchronizer for effectuating data transfer between first and second clock domains by utilizing first and second synchronizer controllers. The first synchronizer controller circuit operates in the first clock domain which has N first clock cycles and the second synchronizer controller circuit operates in the second clock domain which has M second clock cycles, wherein N/M?1. Inversion circuitry inverts a first clock signal associated with the first clock domain to generate an inverted first clock signal which is used in effectuating a SYNC pulse during coincident edges of the inverted first clock signal and a second clock signal associated with the second clock domain.

Abstract: Transferring cache line ownership between processors in a shared memory multi-processor computer system. A request for ownership of a cache line is sent from a requesting processor to a memory unit. The memory unit receives the request and determines which one of a plurality of processors other than the requesting processor has ownership of the requested cache line. The memory sends an ownership recall to that processor. In response to the ownership recall, the other processor sends the requested cache line to the requesting processor, which may send a response to the memory unit to confirm receipt of the requested cache line. The other processor may optionally send a response to the memory unit to confirm that the other processor has sent the requested cache line to the requesting processor. A copy of the data for the requested cache line may, under some circumstances, also be sent to the memory unit by the other processor as part of the response.