Abstract: A method for the identification of peripheral equipment within a digital communication system, particularly a message switching system, having a central data processor as central controller and having a plurality of decentralized input/output processors equipped as subscriber and line sets with memory that control the peripheral equipment, the decentralized input/output processors being respectively in communication via a peripheral interface means with the central data processor. A set address (SA), a set type (ST) and an identifier of the memory capacity of the peripheral equipment are transmitted to the central data processor with the assistance of interface means (PBC), the central data processor subsequently transmitting a set-associated memory load information as memory load call signal via the data bus (DBUS) to the interface means (PBC) and, thus, to the memory (SRM).