Abstract: Register halves are allocated independently when performing register allocation during program compilation, thereby effectively doubling the number of registers which are available for allocation, which in turn may reduce spill code and improve run-time performance. When hardware registers are 64 bits wide, for example, an architecture supporting the present invention provides some number of separate hardware instructions that operate on the 32-bit high-word and/or the 32-bit low word of the hardware registers as if those 32-bit words are separate registers. Such hardware instructions are able to manipulate the register halves independently, leaving the other register half untouched. A register coloring algorithm using in the compilation process is invoked using the number of register halves, instead of the number of hardware registers.

Abstract: Optimizing a program having a plurality of functions using an optimization technique that requires breaking a calling convention. A first function of the plurality of functions is modified as a result of optimizing. A name of the first function is mangled to form a unique first mangled name changing the name of the first function to include, as a result of mangling, first information conveying at least in part how the first function was modified. A second function of the plurality of functions, being a caller of the first function, is also modified to correctly invoke the first function using the unique first mangled name to apply the optimization technique. A compilation tool can, after optimizing, use the first information to take a first action with respect to the first procedure, wherein the compilation tool otherwise would require the calling convention to remain unbroken to take the first action.

Abstract: Register halves are allocated independently when performing register allocation during program compilation, thereby effectively doubling the number of registers which are available for allocation, which in turn may reduce spill code and improve run-time performance. When hardware registers are 64 bits wide, for example, an architecture supporting the present invention provides some number of separate hardware instructions that operate on the 32-bit high-word and/or the 32-bit low word of the hardware registers as if those 32-bit words are separate registers. Such hardware instructions are able to manipulate the register halves independently, leaving the other register half untouched. A register coloring algorithm using in the compilation process is invoked using the number of register halves, instead of the number of hardware registers.

Abstract: A system can include an analyzer module configured to analyze spill code generated by a register allocator to determine that register spill instructions can be paired, wherein paired register spill instructions relate to corresponding register locations in each of a first register set and a second register set and that no instructions between said register spill instructions modify any of said register spill instructions; a rewriter module configured to, based on the determining, modify said register spill instructions as a parallel register spill instruction; and a storage module configured to configure storage of associated register spills in memory so said register spills can be loaded back in parallel into corresponding registers of said first and second register sets based on said modified parallel register spill instruction, wherein the configuration of storage includes allocation of space on a memory stack such that the register spills are double word aligned.

Abstract: Optimizing a program having a plurality of functions. The program is optimized using an optimization technique that requires breaking a calling convention. The first function of the plurality of functions is modified as a result of optimizing. A name of the first function is mangled to form a unique first mangled name. Mangling comprises changing the name. The unique first mangled name includes, as a result of mangling, first information conveying at least in part how the first function was modified. A second function of the plurality of functions, being a caller of the first function, is also modified to correctly invoke first function using the unique first mangled name to apply the optimization technique. A compilation tool can, after optimizing, use the first information to take a first action with respect to the first procedure, wherein the compilation tool otherwise would require the calling convention to remain unbroken in order to take the first action.

Abstract: A system can include an analyzer module configured to analyze spill code generated by a register allocator to determine that register spill instructions can be paired, wherein paired register spill instructions relate to corresponding register locations in each of a first register set and a second register set and that no instructions between said register spill instructions modify any of said register spill instructions; a rewriter module configured to, based on the determining, modify said register spill instructions as a parallel register spill instruction; and a storage module configured to configure storage of associated register spills in memory so said register spills can be loaded back in parallel into corresponding registers of said first and second register sets based on said modified parallel register spill instruction, wherein the configuration of storage includes allocation of space on a memory stack such that the register spills are double word aligned.

Abstract: Embodiments of the present invention provide a design for handling register overflow in a CPU having parallel registers. In an embodiment, spill code generated by a registers allocator may be analyzed to identify register spill instructions that can be associated. Register spill instructions that can be associated may be rewritten as parallel spill instructions, and the corresponding register spills may be configured for storage into memory in a manner permitting them to be loaded back to the registers in parallel.

Abstract: The present invention provides a design for handling register overflow in a parallel register architecture. In an embodiment, spill code generated by a register allocator may be analyzed to identify register spill instructions that can be associated. Register spill instructions that can be associated may be rewritten as parallel spill instructions, and the corresponding register spills may be configured for storage into memory in a manner permitting them to be loaded back to the registers in parallel.