Abstract: An electronic device (10). The device comprises a memory structure (12) comprising an integer M of word storage locations. The device further comprises a write shift register (SRWT) for storing a sequence of bits. The sequence in the write shift register comprises a number of bits equal to a ratio of 1/R1 times the integer M. The device further comprises circuitry (16) for providing a write clock cycle to the write shift register for selected write operations with respect to any of the word storage locations. In response to each write clock cycle, received from the circuitry for providing the write clock cycle, the write shift register shifts the sequence in the write shift register. Further, one bit in the sequence in the write shift register corresponds to an indication of one of the memory word storage locations into which a word will be written. The device further comprises a read shift register (SRRD) for storing a sequence of bits.

Abstract: The invention includes an automated method for instantiation of a plurality of registers within an integrated circuit or integrated circuit device, including the computer-implemented steps of defining a programming language having a plurality of keywords identified with the plurality of registers, creating a control file describing the plurality of registers using the defined programming language, providing a compiling program compatible with the control file, and executing the compiling program to generate from the control file a first set of synthesizable codes containing information on traits of each of the registers. Preferably, the synthesizable codes include RTL codes. In a further embodiment, the invention includes executing the compiler program for generating an address decoder module operative n conjunction with the first set of synthesizable code through a top-level module for instantiation of the address decoder module and the plurality of registers.

Abstract: The invention includes an automated method for instantiation of a plurality of registers within an integrated circuit or integrated circuit device, including the computer-implemented steps of defining a programming language having a plurality of keywords identified with the plurality of registers, creating a control file describing the plurality of registers using the defined programming language, providing a compiling program compatible with the control file, and executing the compiling program to generate from the control file a first set of synthesizable codes containing information on traits of each of the registers. Preferably, the synthesizable codes include RTL codes. In a further embodiment, the invention includes executing the compiler program for generating an address decoder module operative n conjunction with the first set of synthesizable code through a top-level module for instantiation of the address decoder module and the plurality of registers.