Abstract: Dynamic runtime calibration of a processor with respect to a specific voltage regulator that powers the processor or a memory subsystem coupled to the processor can reduce or eliminate the need for guardbands in power management computations. The processor receives a current measurement from the voltage regulator and computes a calibration factor based on the measured value and a stored expected value. The calibration factor can be used in making power management decisions instead of adding the guardband to power readings. A manufacturer or distributor of the processor can compute the stored values with a controlled voltage supply that has a higher precision than typical commercial power supplies used in computing systems. The computed, stored values indicate the expected value, which can be used to determine a calibration factor relative to a voltage regulator of an active system.

Abstract: Dynamic runtime calibration of a processor with respect to a specific voltage regulator that powers the processor or a memory subsystem coupled to the processor can reduce or eliminate the need for guardbands in power management computations. The processor receives a current measurement from the voltage regulator and computes a calibration factor based on the measured value and a stored expected value. The calibration factor can be used in making power management decisions instead of adding the guardband to power readings. A manufacturer or distributor of the processor can compute the stored values with a controlled voltage supply that has a higher precision than typical commercial power supplies used in computing systems. The computed, stored values indicate the expected value, which can be used to determine a calibration factor relative to a voltage regulator of an active system.

Abstract: An apparatus comprising an integrated circuit on a VLSI die, and an embedded micro-controller constructed on the VLSI die, the micro-controller adapted to monitor and control the VLSI environment to optimize the integrated circuit operation. Another embodiment of the invention is directed to a method for monitoring and controlling an integrated circuit comprising providing an embedded micro-controller on a same VLSI die as the integrated circuit, monitoring and controlling a VLSI environment of the integrated circuit with the embedded micro-controller.

Abstract: Devices and methods for managing power on a module are disclosed herein. In one embodiment, a module comprises a first die; a second die; and a power manager. The power manager monitors the power requirements of the first die and the second die and allocates power to the first die and the second die based on the power requirements.

Abstract: Systems and methods for maintaining performance of an integrated circuit are disclosed. One embodiment of a system may comprise a working power limit evaluator that determines a working power limit as a function of at least one performance factor associated with variations that affect performance of the integrated circuit. The system may further comprise a power management system that varies power of the integrated circuit based on the working power limit and an actual power of the integrated circuit to maintain a substantially constant performance.

Abstract: Devices and methods for managing power on a module are disclosed herein. In one embodiment, a module comprises a first die; a second die; and a power manager. The power manager monitors the power requirements of the first die and the second die and allocates power to the first die and the second die based on the power requirements.

Abstract: A system and method that can be utilized to implement voltage adjustment (e.g., for an integrated circuit). In one embodiment, the system comprises a frequency generator that provides a clock signal having a frequency that varies based on an operating voltage. The system also includes a controller that provides a control signal to adjust the operating voltage based on adjustments to the frequency of the clock signal.

Abstract: The present invention is directed to a system and method for measuring a current in an integrated circuit comprising measuring a first output count from a first voltage controlled oscillator (VCO) using a first measurement voltage, simultaneously measuring a second output count from a second VCO using a second measurement voltage, and calculating the current in the integrated circuit using a voltage proportional to a difference between the first and second output counts.

Abstract: A method for calibrating a voltage controlled oscillator (VCO) comprising applying a plurality of known voltages to the input of a VCO, monitoring, for each of the voltages, an output count from the VCO over a set interval, and storing the output counts for each voltage. Also disclosed is a system for calibrating a voltage controlled oscillator (VCO) comprising a plurality of known voltages, wherein the known voltage are connectable to the VCO, and a controller coupled to the output of the VCO, wherein the controller maintains a calibration table of VCO output counts for selected voltage inputs.

Abstract: A system and method for measuring integrated circuit processor power demand comprises calibrating one or more voltage controlled oscillators for use as ammeters, calibrating a calibration current source, wherein the calibration current source draws current through a inherent resistance, calibrating the inherent resistance, and interleaving said calibrations in time with calculating the processor power demand using a voltage that is measured across the inherent resistance.

Abstract: A method of rapidly detecting data errors includes generating a reference syndrome from data bits in a data word, the reference syndrome having at least a first portion and a second portion, generating a partial error code from the data bits and the first portion of the reference syndrome, and initiating an error recovery procedure if the partial error code contains any true values.

Abstract: A method of rapidly detecting data errors includes generating a reference syndrome from data bits in a data word, the reference syndrome having at least a first portion and a second portion, generating a partial error code from the data bits and the first portion of the reference syndrome, and initiating an error recovery procedure if the partial error code contains any true values.

Abstract: A method and apparatus are provided for sensing and temporarily latching data signals from memory cells. According to one embodiment, data signals are sensed from memory cells and temporarily latched on an output signal. During a first phase of a clock cycle, multiple input bit-lines are precharged. Subsequently, a discharged input bit-line is sensed during a second phase of the clock cycle. Responsive to the sensing step, the output signal is set to a first state and maintained for at least one clock cycle. According to another embodiment, a multiple input bit-line detecting circuit includes multiple input bit-lines, precharge logic, and output logic. The multiple input bit-lines are configured to be coupled to a bit-line hierarchy of a memory device. The precharge logic is coupled to each of the input bit-lines and is configured to precharge each of the input bit-lines during a first phase of a clock cycle.