Patents by Inventor Christopher A. Small

Christopher A. Small has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Thread scheduling in chip multithreading processors
    Patent number: 8539491
    Abstract: A thread scheduling technique for assigning multiple threads on a single integrated circuit is dependent on the CPIs of the threads. The technique attempts to balance, to the extent possible, the loads among the processing cores by assigning threads of relatively long-latency (low CPIs) with threads of relatively short-latency (high CPIs) to the same processing core.
    Type: Grant
    Filed: July 26, 2004
    Date of Patent: September 17, 2013
    Assignee: Oracle America, Inc.
    Inventors: Christopher A. Small, Daniel S. Nussbaum, Alexandra Fedorova
  • Thread scheduling in chip multithreading processors
    Patent number: 8490101
    Abstract: A computer system includes an integrated circuit that has a plurality of processing cores fabricated therein and configured to perform operations in parallel. Each processing core is configured to process multiple threads, where a thread is assigned to one of the plurality of processing cores dependent on a cache hit rate of the thread.
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: July 16, 2013
    Assignee: Oracle America, Inc.
    Inventors: Christopher A. Small, Alexandra Fedorova, Daniel S. Nussbaum
  • Cache-aware scheduling for a chip multithreading processor
    Patent number: 7818747
    Abstract: A chip multithreading processor schedules and assigns threads to its processing cores dependent on estimated miss rates in a shared cache memory of the threads. A cache miss rate of a thread is estimated by measuring cache miss rates of one or more groups of executing threads, where at least one of the groups includes the thread of interest. Using a determined estimated cache miss rate of the thread, the thread is scheduled with other threads to achieve a relatively low cache miss rate in the shared cache memory.
    Type: Grant
    Filed: November 3, 2005
    Date of Patent: October 19, 2010
    Assignee: Oracle America, Inc.
    Inventors: Alexandra Fedorova, Christopher A. Small
  • Cache-aware scheduling for a chip multithreading processor
    Patent number: 7487317
    Abstract: A chip multithreading processor schedules and assigns threads to its processing cores dependent on estimated miss rates in a shared cache memory of the threads. A cache miss rate of a thread is estimated by measuring cache miss rates of one or more groups of executing threads, where at least one of the groups includes the thread of interest. Using a determined estimated cache miss rate of the thread, the thread is scheduled with other threads to achieve a relatively low cache miss rate in the shared cache memory.
    Type: Grant
    Filed: November 3, 2005
    Date of Patent: February 3, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Alexandra Fedorova, Christopher A. Small