Abstract: A method includes receiving optical profiles for a plurality of design target features associated with an integrated circuit device and optical profiles for a plurality of test features. An optical proximity correction (OPC) model including a plurality of terms is defined. Each term relates to at least one parameter in the optical profiles. A subset of the model terms is identified as being priority terms. Parameters of the optical profiles of the test features are matched to parameters of the optical profiles of the design target features using the priority terms to generate a set of matched test features. A metrology request is generated to collect metrology data from a test wafer having formed thereon at least a first subset of the matched test features and a second subset of the design target features.

Abstract: A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).

Abstract: A method includes receiving optical profiles for a plurality of design target features associated with an integrated circuit device and optical profiles for a plurality of test features. An optical proximity correction (OPC) model including a plurality of terms is defined. Each term relates to at least one parameter in the optical profiles. A subset of the model terms is identified as being priority terms. Parameters of the optical profiles of the test features are matched to parameters of the optical profiles of the design target features using the priority terms to generate a set of matched test features. A metrology request is generated to collect metrology data from a test wafer having formed thereon at least a first subset of the matched test features and a second subset of the design target features.

Abstract: A method includes providing an initial IC device design, which design has a desired set of electrical characteristics. A layout representation corresponding to the initial device design is generated. A simulation tool is used to determine whether the layout representation corresponds to an IC device design having the desired electrical characteristics. In addition, the variation between structures within IC device designed due to process variations is evaluated using the simulation tool. This variation can be used to determine whether the design is optimized.

Abstract: A method of producing a layout representation corresponding to an integrated circuit (IC) device design can include generating an initial layout representation in accordance with a predetermined set of design rules and simulating how structures within the initial layout representation will pattern on a wafer. Based on the simulation, portions of the layout representation, which include structures demonstrating poor manufacturability and/or portions of the layout representation in which extra manufacturability margin is present, can be identified. Portions of the layout representation including structures demonstrating poor manufacturability and/or in which extra manufacturability margin is present can be modified to optimize the layout representation.

Abstract: A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).

Abstract: A method of generating a metrology recipe includes identifying regions of interest within a device layout. A coordinate list, which corresponds to the identified regions of interest, can be provided and used to create a clipped layout, which can be represented by a clipped layout data file. The clipped layout data file and corresponding coordinate list can be provided and converted into a metrology recipe for guiding one or more metrology instruments in testing a processed wafer and/or reticle. The experimental metrology results received in response to the metrology request can be linked to corresponding design data and simulation data and stored in a queriable database system.

Abstract: A method of producing design rules including generating a plurality of parametrically varying geometric layouts and simulating how each geometric layout will pattern on a wafer. Edges of structures within the simulated geometric layouts can be classified based on manufacturability and design rules can be created to disallow layouts demonstrating poor manufacturability.

Abstract: A method of evaluating a wafer structure formation process includes extracting the outline of an actual mask pattern, and simulating a lithographic process using the actual mask pattern to obtain a simulated wafer structure. The extracting the outline of the actual mask pattern may include, for example, imaging the actual mask using a scanning electron microscope (SEM). A second simulated wafer structure may also be obtained, by simulating the lithographic process using the ideal mask pattern design that was used in producing the actual mask pattern. Thus the relative contribution of mask pattern effects to overall wafer proximity effects may be evaluated by comparing the two simulated wafer structures, either with each other or against a benchmark such as a desired, ideal structure. This information may then be used to generate optical proximity correction (OPC) mask designs which compensate for mask patterning errors and give better wafer performance.

Abstract: The invention includes an apparatus and a method of manufacturing such apparatus including the steps of: forming a layer to be patterned, forming a photosensitive layer over the layer to be patterned, patterning the photosensitive layer to form a pattern including a horizontal line and a vertical line without a space therebetween, transferring the pattern to the layer to be patterned, forming a second photosensitive layer over the pattern, patterning the second photosensitive layer to form a second pattern including a space aligned between the horizontal line and the vertical line, and transferring the second pattern to the layer to be patterned to form a third pattern including a horizontal line and a vertical line with a space therebetween, the space including a width dimension achievable at a resolution limit of lithography.

Abstract: A system and method for generating an illumination intensity profile of an illuminator that forms part of a projection lithography system. Radiation from the illuminator is projected towards an illumination profile mask having a plurality of apertures such that each aperture passes a distinct portion of the radiation. The intensity of each of the distinct portions of radiation is detected and assembled to form the illumination intensity profile.

Abstract: The invention is a method of manufacturing a semiconductor device and such semiconductor device. The semiconductor device includes an integrated circuit pattern including a horizontal line, a vertical line and a space therebetween, the space including a precise width dimension.

Abstract: A method and system of making a mask with a transparent substrate thereon is provided. A first resolution enhancement structure is formed on the first portion of the transparent substrate. A second resolution enhancement structure is formed on a second portion of the transparent substrate, with the second resolution enhancement structure different from the first resolution enhancement structure.

Abstract: A photomask for use in a lithographic process and a method of making a photomask are disclosed. A mask blank including a substrate, a sacrificial conductive layer disposed over the substrate and a radiation shielding layer disposed over the sacrificial conductive layer can be provided. Structures are then formed from the radiation shielding layer to define a pattern. Measurement of parameters associated with the structures are made with a measurement tool and, during the measuring, the sacrificial conductive layer provides a conductive plane to dissipate charge transferred to the mask by the measurement tool.

Abstract: An exemplary Full Phase patterning method involves patterning gates to increase process margins from conventional methods. This technique can define all poly patterns with a phase mask, using only a field or trim mask to resolve conflicts in the phase mask. The trim mask exposes a series of lines that either separates the different phase areas where patterns not desired or minimizes the range of sizes of the phase patterns next to a critical gate area.

Abstract: A technique in which a first boundary region is added to the ends of phase zero (0) pattern defining polygons and a second boundary region is added to the ends of phase 180 pattern. This technique can improve line end pattern definition and improve the manufacturability and patterning process window. The added boundary region balances the light on both sides of the line ends, resulting in a more predictable final resist pattern.

Abstract: A technique in which a first boundary region is added to the ends of phase zero (0) pattern defining polygons and a second boundary region is added to the ends of phase 180 pattern. This technique can improve line end pattern definition and improve the manufacturability and patterning process window. The added boundary region balances the light on both sides of the line ends, resulting in a more predictable final resist pattern.

Abstract: A mask generation method can enhance clear field phase shift masks using a chrome border around phase 180 regions. An exemplary method involves identifying edges of a 180 degree phase pattern, expanding these edges, and merging the expansions with chrome. An alternative method involves oversizing and undersizing phase 180 data, taking the difference, and merging the difference with chrome. The chrome region on the phase mask can improve mask generation by allowing the chrome on the mask to fully define the quartz etch.

Abstract: A mask generation method can enhance clear field phase shift masks using a chrome border around phase 180 regions. An exemplary method involves identifying edges of a 180 degree phase pattern, expanding these edges, and merging the expansions with chrome. An alternative method involves oversizing and undersizing phase 180 data, taking the difference, and merging the difference with chrome. The chrome region on the phase mask can improve mask generation by allowing the chrome on the mask to fully define the quartz etch.

Abstract: A technique in which a first boundary region is added to the ends of phase zero (0) pattern defining polygons and a second boundary region is added to the ends of phase 180 pattern. This technique can improve line end pattern definition and improve the manufacturability and patterning process window. The added boundary region balances the light on both sides of the line ends, resulting in a more predictable final resist pattern.