Abstract: The aspects enable a computing device to allocate memory space to variables during runtime compilation of a software application. A compiler may be modified to identify operations that can be performed on either a main pipe or an alternative pipe, identify chains of related operations that can be performed on either the main pipe or the alternative pipe, identify points in the execution of code at which the number of live values will exceed the number of registers, and choosing a chain of operations as a candidate to be moved to the alternative pipe in order to reduce the number of live values at identified points in the execution of code. The entire chosen chain of operations may be moved to the alternative pipe. The alternative pipe may perform the computations and return the results to the main pipe for execution.

Abstract: The aspects enable a computing device to allocate memory space to variables during runtime compilation of a software application. A first variable associated with a code segment within code being compiled may be identified and assigned a priority tag. A second variable associated with another code segment within the code being compiled may also be assigned a priority tag. A determination may be made regarding whether the first and second variables are contemporaneously live during execution, and whether legal storage location sets for the first and second variables overlap. The assigned priority tags may be used for assigning storage locations to the first and second variables based on the determination.

Abstract: A method for executing an application on multiple nodes includes synchronizing a first clock of a first node and a second clock of a second node, configuring a first hypervisor on the first node to execute a first application domain and a first privileged domain, and configuring a second hypervisor on the second node to execute a second application domain and a second privileged domain. Configuring the hypervisor includes allocating a first number of cycles of the first clock to the first privileged domain. Configuring the second hypervisor includes allocating the first number of cycles of the first clock to the second privileged domain. The method further includes executing the application in the first application domain and the second application domain. The first application domain and the second application domain execute semi-synchronously and the first privileged domain and the second privileged domain execute semi-synchronously.

Abstract: Disclosed are systems, methods and techniques for classifying portions of an area depicted in a digitally encoded map. For example, features in a digitally encoded map may be extracted to identify a component area at least partially bounded by a perimeter formed by structures. One or more egress segments in the perimeter may be identified and characterized. The component area may then be classified based, at least in part, on a proportionality of a length of the egress segment to a size of at least one dimension of the component area.

Abstract: The aspects enable a processor to concurrently execute markup language code (e.g., HTML) having embedded scripting language code (e.g., JAVASCRIPT®) during a page load operation by a browser. A markup language parser parses markup language code until embedded scripting language code is encountered. The segment of embedded scripting language code is extracted for execution by a scripting language engine which proceeds concurrently with speculative parsing of the markup language code. Markup language code generated by execution of scripting language code is evaluated to determine if it is well formed, and a partial rollback of the markup language parse and re-parsing of portions of the markup language code is accomplished if not. Concurrent parsing of markup language code and execution of scripting language code, with partial roll back of the parsing process when necessary, continues until all markup language code has been parsed and all scripting language code has been executed.

Abstract: In the various aspects, a virtual machine operating at the machine layer may use power consumption models to partition object code into portions, identify the relative power efficiencies of the mobile device processors for the various code portions, and route the code portions to the mobile device processors that can perform the operations using the least amount of energy. A dynamic binary translator process may translate the object code portions into an instruction set language supported by the hardware component identified as being preferred. The code portions may be executed and the amount of power consumed may be measured, with the measurements used to generate and/or update performance and power consumption models.

Abstract: In the various aspects, virtualization techniques may be used to reduce the amount of power consumed by execution of applications by power-optimizing the code prior to execution. A dynamic binary translator operating at the machine layer may use a power consumption model to identify code segments that can benefit from optimization and to perform an instruction-sequence to instruction-sequence translation of object code to generate power-optimized object code. Execution hardware may be instrumented with additional circuitry to measure the power consumption characteristics of executing code. The power consumption models may be updated and object code may be regenerated based on the measured the power consumption characteristics of previously executed code. In an aspect, power optimization may be accomplished when the computing device is connected to a battery charger.

Abstract: Described is a system that tracks enregistered memory locations. The system receives program object code that enregisters a memory location (e.g., a set of data at a given memory address) and executes the program code using a thread. Enregistering memory locations involves using additional registers to cache frequently used memory locations while the object code is executing, these additional registers being available on an architecture on which the program executes, but generally not available on an architecture for which the object code was generated. After enregistering the memory location, the system uses a table that identifies enregistered memory locations to track the associated memory address and a thread identifier for the thread. The system checks this table during memory accesses to ensure that other threads attempting to access an enregistered memory location receive a current value for the enregistered memory location.

Abstract: One embodiment of the present invention provides a system that accesses memory locations in an object-addressed memory system. During a memory access in the object-addressed memory system, the system receives an object identifier and an address. The system then uses the object identifier to identify a paged memory object associated with the memory access. Next, the system uses the address and a page table associated with the paged memory object to identify a memory page associated with the memory access. After determining the memory page, the system uses the address to access a memory location in the memory page.

Abstract: The aspects enable a processor to concurrently execute a first serial language code (e.g., HTML) embedding a second serial language code (e.g., JavaScript®) during a page load operation by a browser. A parser parses the first serial language code until a segment of the embedded second serial language code is encountered. The segment of embedded second serial language code is extracted for execution by an execution engine, which proceeds concurrently with speculative parsing of the first serial language code. Code generated by execution of second serial language code is evaluated to determine if it is well formed, and a partial rollback and re-parsing of the first serial language code is performed if the code is not well formed.

Abstract: The aspects enable a processor to concurrently execute markup language code (e.g., HTML) having embedded scripting language code (e.g., JavaScript®) during a page load operation by a browser. A markup language parser parses markup language code until embedded scripting language code is encountered. The segment of embedded scripting language code is extracted for execution by a scripting language engine which proceeds concurrently with speculative parsing of the markup language code. Markup language code generated by execution of scripting language code is evaluated to determine if it is well formed, and a partial rollback of the markup language parse and re-parsing of portions of the markup language code is accomplished if not. Concurrent parsing of markup language code and execution of scripting language code, with partial roll back of the parsing process when necessary, continues until all markup language code has been parsed and all scripting language code has been executed.

Abstract: A system and method are provided for inlining across protection domain boundaries with a system virtual machine. A protection domain comprises a unique combination of a privilege level and a memory address space. The system virtual machine interprets or dynamically compiles not only application code executing under guest operating systems, but also the guest operating systems. For a program call that crosses a protection domain boundary, the virtual machine assembles an intermediate representation (IR) graph that spans the boundary. Region nodes corresponding to code on both sides of the call are enhanced with information identifying the applicable protection domains. The IR is optimized and used to generate instructions in a native ISA (Instruction Set Architecture) of the virtual machine. Individual instructions reveal the protection domain in which they are to operate, and instructions corresponding to different domains may be interleaved.

Abstract: A method for configuring software modules that includes accessing a properties repository that includes a plurality of properties of the execution environment of the computer system. The method further includes generating a configuration file for each software module. Generating a configuration file includes obtaining a generator module defined for the software module, and executing the generator module to instantiate the configuration file for the software module. The generator module is configured to identify a property required for the configuration file, obtain the value for the property from the properties repository, and store the value for the property in the configuration file in accordance with a customized format required by the software module. The method further includes storing the configuration file for each of the software modules.

Abstract: A system and method are provided for inlining a program call between processes executing under separate ISAs (Instruction Set Architectures) within a system virtual machine. The system virtual machine hosts any number of virtual operating system instances, each of which may execute any number of applications. The system virtual machine interprets or dynamically compiles not only application code executing under virtual operating systems, but also the virtual operating systems. For a program call that crosses ISA boundaries, the virtual machine assembles an intermediate representation (IR) graph that spans the boundary. Region nodes corresponding to code on both sides of the call are enhanced with information identifying the virtual ISA of the code. The IR is optimized and used to generate instructions in a native ISA (Instruction Set Architecture) of the virtual machine. Individual instructions are configured and executed (or emulated) to perform as they would within the virtual ISA.

Abstract: A method for metadata management for scalable processes, involving creating a process by a first home processor, wherein the process is associated with a process identification (ID), storing the processor ID and information identifying the first home processor in a global process look-up data structure (GPLD), requesting metadata associated with the process, searching the GPLD to obtain the first home processor of the process using the process ID, and retrieving the metadata associated with the process from the first home processor.

Abstract: A method for executing an application on multiple nodes includes synchronizing a first clock of a first node and a second clock of a second node, configuring a first hypervisor on the first node to execute a first application domain and a first privileged domain, and configuring a second hypervisor on the second node to execute a second application domain and a second privileged domain. Configuring the hypervisor includes allocating a first number of cycles of the first clock to the first privileged domain. Configuring the second hypervisor includes allocating the first number of cycles of the first clock to the second privileged domain. The method further includes executing the application in the first application domain and the second application domain. The first application domain and the second application domain execute semi-synchronously and the first privileged domain and the second privileged domain execute semi-synchronously.

Abstract: The functionality of a virtualization layer interposed between computer system hardware and a plurality of applications can be altered by pluggable extensions. According to one embodiment of the present invention, a virtualization layer is divided into a privileged portion and an unprivileged portion. While the privileged portion remains untouched, the functionality of the unprivileged portion can be modified by one or more pluggable extensions. Furthermore, file images operating on top of the virtualization layer, and in some cases unaware of the virtual nature of the virtualization layer, can be supplemented using pluggable extensions.

Abstract: A system and method for allocating the nearest available physical memory in a distributed, shared memory system. In various embodiments, a processor node may broadcast a memory request to a first subset of nodes connected to it via a communication network. In some embodiments, if none of these nodes is able to satisfy the request, the processor node may broadcast the request to additional subsets of nodes. In some embodiments, each node of the first subset of nodes may be removed from the processor node by one network hop and each node of the additional subsets of nodes may be removed from the processor node by no more than an iteratively increasing number of network hops. In some embodiments, the processor node may send an acknowledgment to one node that can fulfill the request and a negative acknowledgement to other nodes that can fulfill the request.

Abstract: A method for detecting a dependence violation in an application that involves executing a plurality of sections of the application in parallel, and logging memory transactions that occur while executing the plurality of sections to obtain a plurality of logs and a plurality of temporary results, where the plurality of logs is compared while executing the plurality of sections to determine whether the dependence violation exists.

Abstract: A method for executing an application on a plurality of nodes, that includes synchronizing a first clock of a first node of the plurality of nodes and a second clock of a second node of the plurality of nodes, configuring a first hypervisor on the first node to execute a first application domain and a first privileged domain, configuring a second hypervisor on the second node to execute a second application domain and a second privileged domain, and executing the application in the first application domain and the second application domain, wherein the first application domain and the second application domain execute semi-synchronously and the first privileged domain and the second privileged domain execute semi-synchronously.