Abstract: Aspects of the disclosure are directed to an architecture including a dynamic serialization buffer and/or dynamic deserialization buffer coupled between a vector processing unit and a matrix multiplication unit. The dynamic serialization buffer and/or dynamic deserialization buffer allow for streaming any integer of vectors per cycle when performing acceleration of matrix multiplication operations. The matrix multiplication unit receives vectors equivalent to an amount of data from the vector processing unit at an arbitrary rate of vectors per cycle. The matrix multiplication unit processes the vectors to generate resulting vectors that are output at the arbitrary rate.

Abstract: The disclosure provides a self-repairable chip for silent data corruption (SDC) issues. The self-repairable chip is configured to detect data corruption in a plurality of processing units, identifying the defective tiles of the processing units, and repairing the defective tiles by replacing the defective tiles with redundant rows or columns. The self-repairable chip is further configured to determine whether one or more logics where the data corruption occurred must work or may work and replace the defective tiles with redundant rows or columns when the logic where the data corruption occurred may work.

Abstract: A vector processing unit is described, and includes processor units that each include multiple processing resources. The processor units are each configured to perform arithmetic operations associated with vectorized computations. The vector processing unit includes a vector memory in data communication with each of the processor units and their respective processing resources. The vector memory includes memory banks configured to store data used by each of the processor units to perform the arithmetic operations. The processor units and the vector memory are tightly coupled within an area of the vector processing unit such that data communications are exchanged at a high bandwidth based on the placement of respective processor units relative to one another, and based on the placement of the vector memory relative to each processor unit.

Abstract: Methods, systems, and apparatus, including computer-readable storage media for processing block-scaled data on processing devices, where the block size of the data is smaller than the number of implemented processing lanes on the devices. An example process performed by the devices is matrix multiplication. The processing device is configured to load pre-computed scaling factors for static data, and to generate scaling factors for dynamic data as part of the matrix multiplication pipeline for the device. The processing device is configured to cause scaling factors of different blocks of either operand matrix being multiplied to be applied to corresponding blocks during multiplication. The processing device can generate correct matrix multiplication products of block-scaled input, even when the block size is more granular or smaller than the number of processing lanes. Aspects of the disclosure relate to generating scaling factors for input matrices received by a SIMD-configured processing device.

Abstract: The disclosure provides a self-repairable chip for silent data corruption (SDC) issues. The self-repairable chip is configured to detect data corruption in a plurality of processing units, identifying the defective tiles of the processing units, and repairing the defective tiles by replacing the defective tiles with redundant rows or columns. The self-repairable chip is further configured to determine whether one or more logics where the data corruption occurred must work or may work and replace the defective tiles with redundant rows or columns when the logic where the data corruption occurred may work.

Abstract: A vector processing unit is described, and includes processor units that each include multiple processing resources. The processor units are each configured to perform arithmetic operations associated with vectorized computations. The vector processing unit includes a vector memory in data communication with each of the processor units and their respective processing resources. The vector memory includes memory banks configured to store data used by each of the processor units to perform the arithmetic operations. The processor units and the vector memory are tightly coupled within an area of the vector processing unit such that data communications are exchanged at a high bandwidth based on the placement of respective processor units relative to one another, and based on the placement of the vector memory relative to each processor unit.

Abstract: A circuit comprises an input register configured to receive an input vector of elements, a control register configured to receive a control vector of elements, wherein each element of the control vector corresponds to a respective element of the input vector, and wherein each element specifies a permutation of a corresponding element of the input vector, and a permute execution circuit configured to generate an output vector of elements corresponding to a permutation of the input vector. Generating each element of the output vector comprises accessing, at the input register, a particular element of the input vector, accessing, at the control register, a particular element of the control vector corresponding to the particular element of the input vector, and outputting the particular element of the input vector as an element at a particular position of the output vector that is selected based on the particular element of the control vector.

Abstract: Aspects of the disclosure are directed to an architecture including a dynamic serialization buffer and/or dynamic deserialization buffer coupled between a vector processing unit and a matrix multiplication unit. The dynamic serialization buffer and/or dynamic deserialization buffer allow for streaming any integer of vectors per cycle when performing acceleration of matrix multiplication operations. The matrix multiplication unit receives vectors equivalent to an amount of data from the vector processing unit at an arbitrary rate of vectors per cycle. The matrix multiplication unit processes the vectors to generate resulting vectors that are output at the arbitrary rate.

Abstract: Designing a circuit to perform a floating point arithmetic operation by identifying a multiple of parameters that characterize circuits for performing the floating point arithmetic operation and an equation relating the plurality of parameters to a maximum relative backward error parameter, the circuits respectively corresponding to combinations of values for the parameters; specifying a target maximum relative backward error for the floating point arithmetic operation; computing a maximum relative backward error for each of one or more of the combinations of values based on the equation; and when the maximum relative backward error for a respective combination of values is less than the target maximum relative backward error, identifying the circuit corresponding to the maximum relative backward error as a circuit operable to perform the floating point arithmetic operation at a desirable output accuracy.

Abstract: A circuit for performing neural network computations for a neural network comprising a plurality of layers, the circuit comprising: activation circuitry configured to receive a vector of accumulated values and configured to apply a function to each accumulated value to generate a vector of activation values; and normalization circuitry coupled to the activation circuitry and configured to generate a respective normalized value from each activation value.

Abstract: A circuit for transposing a matrix comprising reversal circuitry configured, for each of one or more diagonals of the matrix, to receive elements of the matrix in a first vector and generate a second vector that includes the elements of the matrix in an order that is a reverse of an order of the elements of the matrix in the first vector, and rotation circuitry configured, for each of the one or more diagonals of the matrix, to determine a number of positions by which to rotate the elements of the matrix in the second vector, receive the second vector of elements of the matrix, and generate a third vector that includes the elements of the matrix in the second vector in an order that is a rotation of the elements of the matrix in the second vector by the determined number of positions.

Abstract: In a system including vector registers storing right-hand side data and left-hand side data, first and second matrix staging registers, and a systolic array of processing cells for conducting matrix multiplication operations using the right-hand side data and left-hand side data, one or more processors load the right-hand side data from the vector registers to the first matrix staging register based on an instruction indicating whether to transpose the right-hand side data, load the left-hand side data from the vector registers into the second matrix staging register based on another instruction indicating whether to transpose the left-hand side data, load the right-hand side data from the first matrix staging register into the systolic array, and, in a cycle of the matrix multiplication operation, pass one or more columns of the left-hand side data from the second matrix staging register to a column of the systolic array.

Abstract: In a system including vector registers storing right-hand side data and left-hand side data, first and second matrix staging registers, and a systolic array of processing cells for conducting matrix multiplication operations using the right-hand side data and left-hand side data, one or more processors load the right-hand side data from the vector registers to the first matrix staging register based on an instruction indicating whether to transpose the right-hand side data, load the left-hand side data from the vector registers into the second matrix staging register based on another instruction indicating whether to transpose the left-hand side data, load the right-hand side data from the first matrix staging register into the systolic array, and, in a cycle of the matrix multiplication operation, pass one or more columns of the left-hand side data from the second matrix staging register to a column of the systolic array.

Abstract: A circuit for performing neural network computations for a neural network comprising a plurality of layers, the circuit comprising: activation circuitry configured to receive a vector of accumulated values and configured to apply a function to each accumulated value to generate a vector of activation values; and normalization circuitry coupled to the activation circuitry and configured to generate a respective normalized value from each activation value.

Abstract: A system and method for matrix multiplication using a systolic array configurable between multiple modes of operation. A systolic processor may receive a data type indicator for the matrix multiplication. For a first data type, the systolic processor may load the right-hand side data from the right-hand matrix register into the data processing cells of the systolic array between row 0 and row M?1, and pass the respective row of the left-hand side data through a corresponding row of the systolic array between rows 0 and M?1. For a second data type, the systolic processor may split each element of the left-hand side data and the right-hand side data into respective first and second element halves, and move each element half through a corresponding row of the systolic array between rows 0 and 2M?1.

Abstract: A circuit comprises an input register configured to receive an input vector of elements, a control register configured to receive a control vector of elements, wherein each element of the control vector corresponds to a respective element of the input vector, and wherein each element specifies a permutation of a corresponding element of the input vector, and a permute execution circuit configured to generate an output vector of elements corresponding to a permutation of the input vector. Generating each element of the output vector comprises accessing, at the input register, a particular element of the input vector, accessing, at the control register, a particular element of the control vector corresponding to the particular element of the input vector, and outputting the particular element of the input vector as an element at a particular position of the output vector that is selected based on the particular element of the control vector.

Abstract: A circuit for performing neural network computations for a neural network comprising a plurality of layers, the circuit comprising: activation circuitry configured to receive a vector of accumulated values and configured to apply a function to each accumulated value to generate a vector of activation values; and normalization circuitry coupled to the activation circuitry and configured to generate a respective normalized value from each activation value.

Abstract: A vector processing unit is described, and includes processor units that each include multiple processing resources. The processor units are each configured to perform arithmetic operations associated with vectorized computations. The vector processing unit includes a vector memory in data communication with each of the processor units and their respective processing resources. The vector memory includes memory banks configured to store data used by each of the processor units to perform the arithmetic operations. The processor units and the vector memory are tightly coupled within an area of the vector processing unit such that data communications are exchanged at a high bandwidth based on the placement of respective processor units relative to one another, and based on the placement of the vector memory relative to each processor unit.

Abstract: A circuit comprises an input register configured to receive an input vector of elements, a control register configured to receive a control vector of elements, wherein each element of the control vector corresponds to a respective element of the input vector, and wherein each element specifies a permutation of a corresponding element of the input vector, and a permute execution circuit configured to generate an output vector of elements corresponding to a permutation of the input vector. Generating each element of the output vector comprises accessing, at the input register, a particular element of the input vector, accessing, at the control register, a particular element of the control vector corresponding to the particular element of the input vector, and outputting the particular element of the input vector as an element at a particular position of the output vector that is selected based on the particular element of the control vector.

Abstract: A circuit for performing neural network computations for a neural network comprising a plurality of layers, the circuit comprising: activation circuitry configured to receive a vector of accumulated values and configured to apply a function to each accumulated value to generate a vector of activation values; and normalization circuitry coupled to the activation circuitry and configured to generate a respective normalized value from each activation value.