Abstract: A clock receiver for an integrated circuit includes duty-cycle correction capabilities based on monitoring an average value associated with an internally generated clock signal. An active adjustment circuit within the clock receiver provides correction to each leg of the differential clock signal based on two correction signals. The correction signals are derived from a comparison of the average value associated with the internal clock signal with a target voltage. The target voltage is based on a trip-point of an inverter stage in a logic stage that is driven by the internal clock signal. The closed loop control of the correction signals adjusts the average value of the internal clock signal until it is substantially equal to the target voltage. By straddling the internal clock signal about the trip-point of the inverter stage, the duty-cycle associated with the internal clock signal is adjusted to substantially a 50% duty cycle.

Abstract: An on-chip resistor is calibrated with a sense circuit that compares a resistance associated with an off-chip resistor to the on-chip resistor via a current-mirror circuit and a comparator. A digital counter circuit evaluates the comparison and adjusts its count such that a variable digital control signal is provided to the on-chip resistor circuit. During the calibration of the on-chip resistor circuit, the resistance of the on-chip resistor can be matched to the resistance of the off-chip resistor according to a scaling factor (e.g., 1×, 2×, 2.5×, 10×, etc.) as may be desired. Once the resistance associated with the on-chip resistor circuit is sufficiently adjusted, another on-chip resistor (e.g., a terminating resistor of another circuit) can be adjusted from the counter value. Various other circuits can be disabled during the calibration of the on-chip resistor such that additional sources of error (e.g., supply variation, ground bounce, noise, etc.) are minimized.

Abstract: A circuit for calibrating a coarse channel circuit in a folding analog-to-digital converter circuit. A reference value is input to the coarse channel circuit and an output of the coarse channel circuit is sensed. A parameter of the coarse channel circuit is adjusted until the coarse channel circuit is successfully calibrated.

Abstract: A time interleaved ADC system includes a delay circuit that has a dynamically adjusted speed to achieve uniformly spaced sampling intervals. The adjustment control circuit monitors the sampling pulses associated with sampling time instant for each ADC, and provides one or more control signals to the delay circuit. In one example, the adjustment control circuit employs a phase detector circuit, an integrator circuit, and a dynamic biasing circuit. In this example, the phase detector circuit evaluates the sampling pulses to generate control signals for the integrator circuit, which generates signals that are utilized by the dynamic biasing circuit to adjust the delays associated with the delay circuit. The relative positions of the sampling pulses are controlled by adjusting the delay in the delay circuit.