Patents by Inventor Christopher Allan Poirier
Christopher Allan Poirier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230409392Abstract: An apparatus and method for efficiently managing balanced performance among replicated partitions of an integrated circuit despite loss of functionality due to manufacturing defects. A processing unit includes at least two replicated partitions, each assigned to operation parameters of a respective power domain. The partitions include multiple compute units. The compute units include multiple lanes of execution. Due to a variety of types of manufacturing defects, one or more of the partitions of the processing unit has less than a predetermined number of operational compute units. To balance the throughput of the multiple partitions, a power manager generates both static and dynamic scaling factors based on at least the corresponding number of operational compute units. Using these scaling factors, the power manager adjusts the operation parameters of power domains for the partitions relative to one another.Type: ApplicationFiled: June 20, 2022Publication date: December 21, 2023Inventors: Ashish Jain, Sriram Sundaram, Christopher Allan Poirier, Samuel D. Naffziger
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Patent number: 11201607Abstract: Examples disclosed herein relate to set-reset (SR) latch circuits and methods for manufacturing the same. In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of p-channel field-effect transistors (PFETs) for control circuitry. The PFETs may include first and second PFETs connected to a first node of the inverter storage loop, and third and fourth PFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth PFETs may be connected to a first control input, and gate terminals of the second and third PFETs may be connected to a second control input.Type: GrantFiled: September 4, 2018Date of Patent: December 14, 2021Assignee: Hewlett Packard Enterprise Development LPInventors: Christopher Allan Poirier, Ryan Barnhill, Dacheng Zhou
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Patent number: 10389342Abstract: A comparator includes a resolver controlled by a resolver clock signal and a differential amplifier controlled by a sampling clock signal. The resolver clock signal and the sampling clock signal are such that amplification at the differential amplifier during the reset phase of the resolver clock signal and the reset phase of the sampling clock signal begins during the resolving phase of the resolver.Type: GrantFiled: June 28, 2017Date of Patent: August 20, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Dacheng Zhou, Daniel Alan Berkram, Ryan Barnhill, Christopher Allan Poirier, Christopher Wilson
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Patent number: 10270444Abstract: According to examples, an apparatus may include a field effect transistor (FET), a driver to receive an input signal and to output a driver output signal, and a gate to receive the input signal. The apparatus may also include a delay element to receive the driver output signal and to output a delayed signal to the gate after a delay from receipt of the driver output signal, in which the gate is to output a gate output signal to the FET in response to receipt of the input signal and the delayed signal, and in which receipt of the gate output signal by the FET drives the FET to provide a boost to the driver output signal.Type: GrantFiled: April 4, 2018Date of Patent: April 23, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Edward James Luckett, Christopher Allan Poirier
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Publication number: 20190007037Abstract: A comparator includes a resolver controlled by a resolver clock signal and a differential amplifier controlled by a sampling clock signal. The resolver clock signal and the sampling clock signal are such that amplification at the differential amplifier during the reset phase of the resolver clock signal and the reset phase of the sampling clock signal begins during the resolving phase of the resolver.Type: ApplicationFiled: June 28, 2017Publication date: January 3, 2019Inventors: Dacheng Zhou, Daniel Alan Berkram, Ryan Barnhill, Christopher Allan Poirier, Christopher Wilson
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Publication number: 20180375501Abstract: Examples disclosed herein relate to set-reset (SR) latch circuits and methods for manufacturing the same. In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of p-channel field-effect transistors (PFETs) for control circuitry. The PFETs may include first and second PFETs connected to a first node of the inverter storage loop, and third and fourth PFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth PFETs may be connected to a first control input, and gate terminals of the second and third PFETs may be connected to a second control input.Type: ApplicationFiled: September 4, 2018Publication date: December 27, 2018Inventors: Christopher Allan Poirier, Ryan Barnhill, Dacheng Zhou
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Patent number: 10075150Abstract: Examples disclosed herein relate to set-reset (SR) latch circuits and methods for manufacturing the same. In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of p-channel field-effect transistors (PFETs) for control circuitry. The PFETs may include first and second PFETs connected to a first node of the inverter storage loop, and third and fourth PFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth PFETs may be connected to a first control input, and gate terminals of the second and third PFETs may be connected to a second control input.Type: GrantFiled: August 3, 2016Date of Patent: September 11, 2018Assignee: Hewlett Packard Enterprise Development LPInventors: Christopher Allan Poirier, Ryan Barnhill, Dacheng Zhou
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Publication number: 20180041199Abstract: Examples disclosed herein relate to set-reset (SR) latch circuits and methods for manufacturing the same. In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of p-channel field-effect transistors (PFETs) for control circuitry. The PFETs may include first and second PFETs connected to a first node of the inverter storage loop, and third and fourth PFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth PFETs may be connected to a first control input, and gate terminals of the second and third PFETs may be connected to a second control input.Type: ApplicationFiled: August 3, 2016Publication date: February 8, 2018Inventors: Christopher Allan Poirier, Ryan Barnhill, Dacheng Zhou
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Patent number: 9323316Abstract: In one embodiment, the present invention includes a method for determining whether a number of stalled cores of a multicore processor is greater than a stall threshold. If so, a recommendation may be made that an operating frequency of system agent circuitry of the processor be increased. Then based on multiple recommendations, a candidate operating frequency of the system agent circuitry can be set. Other embodiments are described and claimed.Type: GrantFiled: March 13, 2012Date of Patent: April 26, 2016Assignee: Intel CorporationInventors: Malini K. Bhandaru, Ankush Varma, James R. Vash, Monica Wong-Chan, Eric J. Dehaemer, Christopher Allan Poirier, Sr., Scott P. Bobholz
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Publication number: 20140208141Abstract: In one embodiment, the present invention includes a method for determining whether a number of stalled cores of a multicore processor is greater than a stall threshold. If so, a recommendation may be made that an operating frequency of system agent circuitry of the processor be increased. Then based on multiple recommendations, a candidate operating frequency of the system agent circuitry can be set. Other embodiments are described and claimed.Type: ApplicationFiled: March 13, 2012Publication date: July 24, 2014Inventors: Malini K. Bhandaru, Ankush Varma, James R. Vash, Monica Wong-Chan, Eric J. Dehaemer, Christopher Allan Poirier, SR., Scott P. Bobholz
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Patent number: 6281710Abstract: An integrated circuit chip includes a domino logic gate, circuitry for selectively latching a logic output signal of the gate and an enable source for the gate. The enable source and gate positions on the chip and a clock driving the chip has a frequency such that the enable signal arrives late at the logic gate during the evaluate phase of each clock cycle. The circuitry for selectively latching is constructed so that the domino logic gate is evaluated or latched during the same clock cycle that the enable signal is derived despite the aforementioned positions and frequency.Type: GrantFiled: December 17, 1999Date of Patent: August 28, 2001Assignee: Hewlett-Packard CompanyInventors: Christopher Allan Poirier, Samuel D Naffziger
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Patent number: 6265897Abstract: A pseudo-NMOS logic gate of an integrated circuit chip is enabled for a time interval that is substantially less than one-half a clock cycle of the integrated circuit. A latch responds to an output signal of the pseudo-NMOS logic gate for a period that is simultaneous with or slightly less than the time while the pseudo-NMOS logic gate is enabled. The latch derives an output signal commensurate with the output signal of the pseudo-NMOS logic gate while the pseudo-NMOS logic gate is enabled, until the next clock cycle occurs.Type: GrantFiled: December 17, 1999Date of Patent: July 24, 2001Assignee: Hewlett-Packard CompanyInventors: Christopher Allan Poirier, Samuel D Naffziger, Wayne Dervon Kever