Abstract: A method for detecting bypass error conditions in a load/store unit of a superscalar processor includes determining whether a load instruction has executed out-of-order with respect to an executing store instruction when a real address to a word boundary of the load instruction and a real address to a word boundary of the executing store instruction match, and identifying a bypass error condition for the load instruction when the load instruction has executed out-of-order with respect to the executing store instruction. In a system aspect, the system includes a load queue, detection logic, and completion logic. The load queue includes a real page number buffer for storing a real address to a word boundary for each executed load instruction. The detection logic compares real addresses to a word boundary for a load instruction against an executing store instruction and compares a program order of the load instruction and the executing store instruction when the real addresses to a word boundary match.

Abstract: A load queue is provided in a load/store unit of a superscalar processor that includes a real page number buffer for storing a real page number for each instruction entry in the load queue. The load queue also includes a real page number comparator coupled to the real page number buffer for comparing executing load instruction entries with queued load instruction entries in the load queue. The load queue further includes a cache line modified register coupled to the data cache. The cache line modified register marks the queued load instruction entries when a cache line of the data cache addressed by the queued load instruction entry has been modified. In a preferred embodiment, when the executing load instruction is out of program order with respect to one of the queued load instructions, and the modified cache line register has marked the queued load instruction, the load queue signals a sequencer unit to cancel the queued load instruction.