Abstract: A semiconductor device is provided including NS-FETs in which the active area module, the shallow trench isolation module and the gate module are eliminated from the processing of the semiconductor device. The elimination of these modules makes the overall process easier and aids in reducing the cost of manufacturing the semiconductor device.

Abstract: Systems, methods, and computer program products can determine wear, damage, change, or other characteristics of a portion of a front linkage of an excavator. The systems, methods, and computer program products can comprise determining, based on signals from at least one sensor of the excavator, that the excavator is in a predetermined state to weigh at least a portion of the front linkage of the excavator; determining a weight of the portion of the front linkage of the excavator under a condition that the excavator is in the state to weigh the portion of the front linkage of the excavator; determining that the determined weight of the portion of the front linkage is outside of a predetermined weight range; and electronically outputting information regarding a further action to be taken with respect to the portion of the front linkage of the excavator.

Abstract: Embodiments of present invention provide an interconnect structure. The interconnect structure includes a first metal line having a lower portion and an upper portion of different material composition, sidewalls of the lower portion of the first metal line being vertically aligned with sidewalls of the upper portion of the first metal line; a second metal line having a lower portion and an upper portion of different material composition, sidewalls of the lower portion of the second metal line being vertically aligned with sidewalls of the upper portion of the second metal line; a dielectric liner lining sidewalls of the lower and upper portions of the first metal line and sidewalls of the lower and upper portions of the second metal line; and an isolation layer between the first and second metal lines, the isolation layer including an airgap. A method of forming the same is also provided.

Abstract: A novel bevel etch sequence for embedded metal contamination removal from BEOL wafers is provided. In one aspect, a method of processing a wafer includes: performing a bevel dry etch to break up layers of contaminants with embedded metals which, post back-end-of line metallization, are deposited on a bevel of the wafer, which forms a damaged layer on surfaces of the wafer, and then performing a sequence of wet etches, following the bevel dry etch, to render the bevel of the wafer substantially free of contaminants, wherein the sequence of wet etches includes etching the damaged layer to undercut and lift-off any remaining contaminants. A wafer, processed in this manner, having a bevel that is substantially free of contaminants is also provided.

Abstract: A device comprises a first interconnect structure, a second interconnect structure, a first cell comprising a first transistor, a second cell comprising a second transistor, a first contact connecting a source/drain element of the first transistor to the first interconnect structure, and second contact connecting a source/drain element of the second transistor to the second interconnect structure. The first cell is disposed adjacent to the second cell with the first transistor disposed adjacent to the second transistor. The first and second cells are disposed between the first and second interconnect structures.

Abstract: Embodiments of present invention provide a method of forming a semiconductor structure. The method includes forming a passive device area and a logic device area on a substrate; forming a diffusion break between the passive device area and the logic device area, wherein the diffusion break extends into the substrate; removing a portion of the substrate to expose a bottom portion of the diffusion break; covering a first portion of the substrate underneath the passive device area and the bottom portion of the diffusion break with a hard mask; selectively removing a second portion of the substrate to expose at least a portion of a bottom surface of the logic device area; and depositing a backside interlevel dielectric (BILD) layer to cover the portion of the bottom surface of the logic device area. The semiconductor structure formed thereby is also provided.

Abstract: A semiconductor device including stacked field effect transistors (FETs) is provided. The stacked FETs are formed utilizing a process that optimizes the thermal budget without negatively impacting the frontside and/or backside contact structures. The stacked can be designed to have different work function metals and a frontside/backside deep via structure can be provided that has a low area resistance.

Abstract: A microelectronic structure includes a first row of stack nano devices that includes a plurality of a first stacked nano FET devices and a second row of stack nano devices that includes a plurality of a second stacked nano FET devices. Each of the plurality of first nano stacked FET devices and each of the plurality of second stacked FET devices includes an upper stack transistor and a lower stack transistor. A gate cut located between the first row of stacked nano devices and the second row stacked nano devices. An interconnect located within gate cut. The interconnect is connected to a source/drain of one of the lower stacked transistors and the interconnect includes a non-uniform backside surface.

Abstract: Seat belt web retractors having web locking mechanisms are described herein. In some embodiments, a seat belt web retractor includes an inertial locking mechanism operably coupled to a spool about which a seat belt web is wound. The web retractor further includes a web locking mechanism operably coupled to the inertial locking mechanism. The web locking mechanism can include a driving member that is actuated by engagement of the inertial locking mechanism with the web spool in response to rapid extraction of the web from the retractor. Actuation of the driving member drives first and second clamping portions toward each other, thereby clamping the web in between the clamping members and restraining the web from further movement out of the retractor.

Abstract: A semiconductor structure includes logic device and passive device regions. The logic device region includes field effect transistors (FETs) having a gate structure and a source/drain region disposed on opposing sides of the gate structure. At least one source/drain region extends within a buried dielectric layer for electrically connecting a FET to a backside power rail (BPR). The passive device region includes passive devices disposed on a first side of a first semiconductor layer. A second semiconductor layer is disposed above a second side of the first semiconductor layer opposing the first side. A backside interlevel dielectric (BILD) is above the second semiconductor layer and the buried dielectric layer. The BPR is embedded within the BILD in the logic device region. A top surface of the BILD in the passive device region is coplanar with a top surface of the BPR and the BILD in the logic device region.

Abstract: This disclosure describes, in part, systems and techniques for monitoring linkage joints of machines, such as earth-moving machines, using on-board sensors of the machines to identify linkage joints at risk of galling. The systems and techniques involve gathering sensor data and determining a galling risk score for each linkage joint. The galling risk score may then be used to alert an operator and/or maintenance system to determine when to take remedial action and/or perform maintenance while also avoiding costly downtime from galling failures.

Abstract: An arthroscopic surgery system for assisting a surgeon in performing surgery comprising: a frame configurable to extend above or beside at least a portion of a patient to be operated; and one or more surgical arms extending from the frame, wherein each surgical arm is configured to work with a variety of different arthroscopic instruments; wherein the one or more surgical arms are arranged to assist a surgeon when performing surgery and wherein the surgical arms and attached arthroscopic instruments are controllable by the surgeon whilst performing surgery on the patient.

Abstract: An ESD protection device is disclosed that uses a BSPDN to provide potential(s) to the ESD protection device. The utilization of the BSPDN reduces resistance drops induced during high current ESD events, which results in robust ESD protection. The utilization of the BSPDN also reduces the footprint area of the ESD protection circuit relative to known ESD protection devices that utilize respective frontside contacts to VDD, VSS, and I/O. Further, the disclosed ESD protection circuit may utilize the same or similar structures as that are used by microdevices (e.g., transistors, or the like) within the semiconductor IC device, which may decrease fabrication complexities thereof.

Abstract: An anchor assembly includes: an elongate and flexible anchoring implant for inserting into a bore of bone or tissue, the implant having proximal and distal ends with sidewalls extending therebetween, a suture having: first and second segments between the proximal and distal ends of the implant and, passed through a first and second side wall portions of the implant, respectively; A bridging loop between the two segments, and at or adjacent an in-use upper portion of the implant that includes the proximal end; wherein each of the segments has respective terminal ends of the suture extending from the implant; Applying tension to the terminal ends, when implant is in bone or tissue, causes the proximal end to be drawn towards the distal end to effect change of the implant shape from elongate and radially narrow into axially shortened and radially extended configurations to deploy the implant in the bore.

Abstract: A microelectronic device including a first nanosheet transistors adjacent to a second nanosheet transistor. The first nanosheet transistor includes a plurality of first nanosheets, and the second nanosheet transistor includes a plurality of second nanosheets. A source/drain located between the first nanosheet transistor and second nanosheet transistor. A first gate wraps around the plurality of first nanosheets. A second gate wraps around the plurality of second nanosheets. A first upper spacer located adjacent to the first gate, where the first upper spacer is in contact with at least three sides of the first gate. A second upper spacer located adjacent to the second gate, where the second upper spacer is in contact with at least three sides of the second gate. A backside interconnect connected to the source/drain, where the backside interconnect is in contact with the first upper spacer and the second upper spacer.

Abstract: A semiconductor structure is presented including a metal layer having a first pattern, a metal bridge located within the first pattern, at least one via disposed on a portion of the metal layer such that the metal bridge extends to a top surface of the at least one via, and a metal cap disposed directly on top of the at least one via disposed on the portion of the metal layer.

Abstract: An exemplary embodiment of the present disclosure provides a polyurethane core for use in a floor or wall panel, the core comprising a polyol made, at least in part, from one or more recycled materials, and an isocyanate.

Abstract: A method of making a back-end-of-line (BEOL) component includes filling spaces in a layer of metal material and a layer of hardmask material with a layer of scaffolding material. The method further includes forming at least one plug on top of the layer of metal material such that the at least one plug is integrally formed with the layer of scaffolding material. The method further includes removing the layer of hardmask material such that a top surface of the layer of metal material is exposed except where the at least one plug is formed on top of the layer of metal material. The method further includes recessing the layer of metal material where the top surface of the layer of metal material is exposed. The method further includes removing the scaffolding material.

Abstract: An exemplary embodiment of the present disclosure provides a polyurethane core for use in a floor or wall panel, the core comprising a polyol made, at least in part, from one or more recycled materials, and an isocyanate.

Abstract: A bone fixation system for bone repair, the system comprising a bone fixation plate with upper and lower surfaces and at least one opening formed on the upper and lower surfaces to form a passage extending from the upper surface to the lower surface to receive a bone screw. The passage is defined by one or more non-threaded inner walls extending from the upper surface to the lower surface. At interference portions, the passage has a width between the walls smaller than the diameter of the head of the bone screw to achieve interference between the head of the bone screw and the inner walls at interference portions to lock the bone screw within the passage upon its insertion into the passage at a variable angle of rotation relative to a longitudinal axis of the passage.