Abstract: This disclosure relates to a quantum circuit for quantum approximate optimisation over permutations of a set of elements. Encoding logic encodes each of the elements into multiple quantum registers as a binary number to represent a permutation of the set of elements by storing the binary number of each of the elements in an order according to the permutation. A network of multi-qubit quantum exponential swap operations operates between the multiple qubits of two registers and generates a superposition of two permutations by generating a superposition of two binary numbers by generating a superposition of the multiple qubits of the two quantum registers. An evaluation quantum circuit represents a problem Hamiltonian and distinguishes quantum states of the superposition generated by the network. The network and the evaluation quantum circuit amplify desirable quantum states and suppress undesirable quantum states to optimise over the permutations.

Abstract: A mini-fluidics cassette, for detection of at least one analyte in a sample, comprising, at least one sample inlet port, at least one reagent inlet port, at least one outlet port, at least one channel extending between said at least one sample inlet port and said at least one outlet port, at least one insertion port for a fiber optic cable light source, at least one insertion port for a fiber optic cable spectrophotometer distant said at least one insertion port for a fiber optic cable light source, wherein said at least one insertion port for a fiber optic cable light source and said at least one insertion port for a fiber optic cable spectrophotometer forms part of the at least one channel, and is proximate said at least one outlet port and forms at least one reading cell/path length for light from said fiber optic cable light source to said fiber optic cable spectrophotometer port.

Abstract: The invention relates to embodiments of a device for use in a dynamic network. Said device (100) comprises a network interface (102) for integration into an overlay network topology. A data processing unit (104) is connected to the network interface (102) and is designed to transmit and/or receive data via the network interface (102). A functional unit (106) is coupled to the data processing unit (104).

Abstract: A mini-fluidics cassette, for detection of at least one analyte in a sample, comprising, at least one sample inlet port, at least one reagent inlet port, at least one outlet port, at least one channel extending between said at least one sample inlet port and said at least one outlet port, at least one insertion port for a fiber optic cable light source, at least one insertion port for a fiber optic cable spectrophotometer distant said at least one insertion port for a fiber optic cable light source, wherein said at least one insertion port for a fiber optic cable light source and said at least one insertion port for a fiber optic cable spectrophotometer forms part of the at least one channel, and is proximate said at least one outlet port and forms at least one reading cell/path length for light from said fiber optic cable light source to said fiber optic cable spectrophotometer port.

Abstract: Disclosed are systems and methods for energy management and facility retrofit option selection. The methods may be used to select between various retrofit options and may be used to provide return information to each participant in a retrofit project, including public and private participants.

Abstract: An apparatus for processing data includes a processor operable in a plurality modes including at least one secure mode being a mode in a secure domain and at least one non-secure mode being a mode in a non-secure domain. When the processor is executing a program in a secure mode the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. The processor is responsive to one or more exception conditions for triggering exception processing using an exception handler. The processor is operable to select the exception handler from among a plurality of possible exception handlers in dependence upon whether the processor is operating in the secure domain or the non-secure domain.

Abstract: A data processing system including a processor operable in a plurality of modes and in either a secure domain or a non-secure domain. The system includes at least one secure mode being a mode in the secure domain, at least one non-secure mode being a mode in the non-secure domain, and a monitor mode. When the processor is executing a program in a secure mode the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. Switching between the secure and non-secure modes takes place via the monitor mode and the processor is operable at least partially in the monitor mode to execute a monitor program managing switching between the secure and non-secure modes.

Abstract: A processor may utilise two operating systems (Non-Secure, Secure) between which calls may be made. In order that a second operating system can track task switches made by a first operating system, each time a call is made to the second operating system, this call includes an identifier to enable discrimination between the task which was executing on the first operating system when that call was made. The identifier can be a call identifier and/or a target thread identifier and may include further parameters.

Abstract: An apparatus for processing data includes a processor operable in a plurality modes including at least one secure mode being a mode in a secure domain and at least one non-secure mode being a mode in a non-secure domain. When the processor is executing a program in a secure mode the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. The processor is responsive to one or more exception conditions for triggering exception processing using an exception handler. The processor is operable to select the exception handler from among a plurality of possible exception handlers in dependence upon whether the processor is operating in the secure domain or the non-secure domain.

Abstract: A processor may utilise two operating systems (Non-Secure, Secure) between which calls may be made. In order that a second operating system can track task switches made by a first operating system, each time a call is made to the second operating system, this call includes an identifier to enable discrimination between the task which was executing on the first operating system when that call was made. The identifier can be a call identifier and/or a target thread identifier and may include further parameters.

Abstract: An apparatus for processing data includes a processor operable in a plurality modes including at least one secure mode being a mode in a secure domain and at least one non-secure mode being a mode in a non-secure domain. When the processor is executing a program in a secure mode the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. The processor is responsive to one or more exception conditions for triggering exception processing using an exception handler. The processor is operable to select the exception handler from among a plurality of possible exception handlers in dependence upon whether the processor is operating in the secure domain or the non-secure domain.

Abstract: In a data processing system using multiple operating systems, an interrupt which itself may be interrupted by a subsequent interrupt which will be serviced in a different operating system, guards itself against being overlooked when that subsequent interrupt has been handled by starting a stub interrupt handling routine in that other operating system before executing the main handling routine in the originating operating system. Thus, the stub interrupt handling routine will be recognised in the other operating system irrespective of other interrupt events which may occur and accordingly the interrupted interrupt handling may be restarted.

Abstract: A high throughput chemical handling system includes a chemical storage module, a transport module, and one or more liquid handling modules. The transport module may implement parallel chemical transport, and the system may include a plurality of asynchronously operable liquid handling modules coupled to the parallel transport module.

Abstract: A data processing system includes a processor that can operate in a plurality of modes and in either a secure domain or a non-secure domain. At least one secure mode is a mode in the secure domain, and at least one non-secure mode is a mode in the non-secure domain. When the processor is executing a program in a secure mode and that program has access to secure data which is not accessible when the processor is operating in a non-secure mode, the processor is responsive to exception conditions for triggering exception processing. Specifically, the processor is responsive to a parameter specifying which of the exceptions should be handled by a secure mode exception handler executing in a secure mode and which should be handled by an exception handler executing in a mode within a current one of the secure domain and the non-secure domain when that exception occurs.

Abstract: In a system supporting more than one operating system, a data processing thread executing on a first operating system may be subject to an interrupt which triggers interrupt handling on a second operating system. When that interrupt handling is completed on the second operating system, the first operating system is resumed using a return interrupt. The return interrupt specifies the data processing thread which is active on the second operating system such that an appropriate task switch or resumption may be made on the first operating system. The technique is particularly well suited to systems utilising a secure operating system and a non-secure operating system executing on the same hardware.

Abstract: There is a provided a data processing system comprising: a processor operable in a plurality of modes and either a secure domain or a non-secure domain including: at least one secure mode being a mode in said secure domain; and at least one non-secure mode being a mode in said non-secure domain; wherein when said processor is executing a program in a secure mode said program has access to secure data which is not accessible when said processor is operating in a non-secure mode; and wherein said processor is responsive to a switching request to initiate a switch between a secure mode and a non-secure mode under control of a mode switching program starting at a location specified by an exception vector associated with said switching request.

Abstract: An adjustable lock assembly that can be used with a sliding window or a sliding door to limit the complete opening of, brace completely shut, or both. The lock assembly can include a first body slidably telescoped with a second body. An affixation device affixes the length of the lock assembly to a selected length. A cuff is disposed around a connection joint defined between the first and second bodies.

Abstract: An apparatus for processing data, the apparatus comprising: a processor operable in a plurality of modes and either a secure domain or a non-secure domain including at least one secure mode being a mode in the secure domain; and at least one non-secure mode being a mode in the non-secure domain. When the processor is executing a program in a secure mode, the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. The processor further includes a non-secure translation table base address register and a secure translation table base address register operable in the non-secure and secure domain, respectively, to indicate a region of memory storing either non-secure or secure domain memory mapping data defining how virtual addresses are translated to physical addresses within either the non-secure or secure domain.

Abstract: A data processing apparatus is operable in a plurality of modes and in either a secure domain or a non-secure domain. When operating in a secure mode within the secure domain a program has access to secure data which is not accessible when the processor is operating in a non-secure mode. A vectored interrupt controller is provided to generate an exception handler address in response to an occurrence of an except condition. The vectored interrupt controller is programmable with parameters specifying for each exception condition whether an exception handler in the secure or the non-secure domain should be triggered and an exception handler address for use if the exception occurs when in the appropriate domain. The vectored interrupt controller also includes a parameter specifying a domain switching exception handler address for use if the exception condition occurs when the processor is not in the appropriate domain.

Abstract: A chemical solution distribution system and method that includes or employs a plurality of liquid handlers where each of the liquid handlers includes a movable table that engages a sample multiwell plate and can align pipettes of the station with different subsets of wells of the multiwell plate where the number of wells of the multiwell plate is a multiple of the number of pipettes of the head of the pipette station. The system further includes and employs four different pumps to enable the system and method to supply four different solutions to wash stations of each of the four liquid handlers.