Patents by Inventor Christopher Bentley

Christopher Bentley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10603661
    Abstract: A mini-fluidics cassette, for detection of at least one analyte in a sample, comprising, at least one sample inlet port, at least one reagent inlet port, at least one outlet port, at least one channel extending between said at least one sample inlet port and said at least one outlet port, at least one insertion port for a fiber optic cable light source, at least one insertion port for a fiber optic cable spectrophotometer distant said at least one insertion port for a fiber optic cable light source, wherein said at least one insertion port for a fiber optic cable light source and said at least one insertion port for a fiber optic cable spectrophotometer forms part of the at least one channel, and is proximate said at least one outlet port and forms at least one reading cell/path length for light from said fiber optic cable light source to said fiber optic cable spectrophotometer port.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: March 31, 2020
    Assignee: Narwhal Analytical Corporation
    Inventors: Andrew Laursen, Christopher Bentley, Bahar Ameri
  • Publication number: 20170353558
    Abstract: The invention relates to embodiments of a device for use in a dynamic network. Said device (100) comprises a network interface (102) for integration into an overlay network topology. A data processing unit (104) is connected to the network interface (102) and is designed to transmit and/or receive data via the network interface (102). A functional unit (106) is coupled to the data processing unit (104).
    Type: Application
    Filed: December 23, 2015
    Publication date: December 7, 2017
    Inventor: Christopher Bentley
  • Publication number: 20170239655
    Abstract: A mini-fluidics cassette, for detection of at least one analyte in a sample, comprising, at least one sample inlet port, at least one reagent inlet port, at least one outlet port, at least one channel extending between said at least one sample inlet port and said at least one outlet port, at least one insertion port for a fiber optic cable light source, at least one insertion port for a fiber optic cable spectrophotometer distant said at least one insertion port for a fiber optic cable light source, wherein said at least one insertion port for a fiber optic cable light source and said at least one insertion port for a fiber optic cable spectrophotometer forms part of the at least one channel, and is proximate said at least one outlet port and forms at least one reading cell/path length for light from said fiber optic cable light source to said fiber optic cable spectrophotometer port.
    Type: Application
    Filed: August 26, 2014
    Publication date: August 24, 2017
    Inventors: Andrew Laursen, Christopher Bentley, Bahar Ameri
  • Publication number: 20140081711
    Abstract: Disclosed are systems and methods for energy management and facility retrofit option selection. The methods may be used to select between various retrofit options and may be used to provide return information to each participant in a retrofit project, including public and private participants.
    Type: Application
    Filed: August 21, 2013
    Publication date: March 20, 2014
    Applicant: CLEAN MARKETS, LLC
    Inventors: Ellen Lutz, Christopher Bentley
  • Patent number: 7949866
    Abstract: An apparatus for processing data includes a processor operable in a plurality modes including at least one secure mode being a mode in a secure domain and at least one non-secure mode being a mode in a non-secure domain. When the processor is executing a program in a secure mode the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. The processor is responsive to one or more exception conditions for triggering exception processing using an exception handler. The processor is operable to select the exception handler from among a plurality of possible exception handlers in dependence upon whether the processor is operating in the secure domain or the non-secure domain.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: May 24, 2011
    Assignee: ARM Limited
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier
  • Patent number: 7849310
    Abstract: A data processing system including a processor operable in a plurality of modes and in either a secure domain or a non-secure domain. The system includes at least one secure mode being a mode in the secure domain, at least one non-secure mode being a mode in the non-secure domain, and a monitor mode. When the processor is executing a program in a secure mode the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. Switching between the secure and non-secure modes takes place via the monitor mode and the processor is operable at least partially in the monitor mode to execute a monitor program managing switching between the secure and non-secure modes.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: December 7, 2010
    Assignee: ARM Limited
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier
  • Patent number: 7661104
    Abstract: A processor may utilise two operating systems (Non-Secure, Secure) between which calls may be made. In order that a second operating system can track task switches made by a first operating system, each time a call is made to the second operating system, this call includes an identifier to enable discrimination between the task which was executing on the first operating system when that call was made. The identifier can be a call identifier and/or a target thread identifier and may include further parameters.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: February 9, 2010
    Assignee: ARM Limited
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastian Brochier, David Hennah Mansell, Dominic Hugo Symes
  • Patent number: 7661105
    Abstract: An apparatus for processing data includes a processor operable in a plurality modes including at least one secure mode being a mode in a secure domain and at least one non-secure mode being a mode in a non-secure domain. When the processor is executing a program in a secure mode the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. The processor is responsive to one or more exception conditions for triggering exception processing using an exception handler. The processor is operable to select the exception handler from among a plurality of possible exception handlers in dependence upon whether the processor is operating in the secure domain or the non-secure domain.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: February 9, 2010
    Assignee: ARM Limited
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier
  • Publication number: 20090320048
    Abstract: A processor may utilise two operating systems (Non-Secure, Secure) between which calls may be made. In order that a second operating system can track task switches made by a first operating system, each time a call is made to the second operating system, this call includes an identifier to enable discrimination between the task which was executing on the first operating system when that call was made. The identifier can be a call identifier and/or a target thread identifier and may include further parameters.
    Type: Application
    Filed: November 17, 2003
    Publication date: December 24, 2009
    Applicant: ARM LIMITED
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier, David Hennah Mansell, Dominic Hugo Symes
  • Publication number: 20090259846
    Abstract: An apparatus for processing data includes a processor operable in a plurality modes including at least one secure mode being a mode in a secure domain and at least one non-secure mode being a mode in a non-secure domain. When the processor is executing a program in a secure mode the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. The processor is responsive to one or more exception conditions for triggering exception processing using an exception handler. The processor is operable to select the exception handler from among a plurality of possible exception handlers in dependence upon whether the processor is operating in the secure domain or the non-secure domain.
    Type: Application
    Filed: March 20, 2009
    Publication date: October 15, 2009
    Applicant: ARM Limited
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephanie Eric Sebastien Brochier
  • Patent number: 7448050
    Abstract: In a data processing system using multiple operating systems, an interrupt which itself may be interrupted by a subsequent interrupt which will be serviced in a different operating system, guards itself against being overlooked when that subsequent interrupt has been handled by starting a stub interrupt handling routine in that other operating system before executing the main handling routine in the originating operating system. Thus, the stub interrupt handling routine will be recognised in the other operating system irrespective of other interrupt events which may occur and accordingly the interrupted interrupt handling may be restarted.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: November 4, 2008
    Assignee: ARM Limited
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier, Michael Robert Nonweiler, Dominic Hugo Symes
  • Publication number: 20080226498
    Abstract: A high throughput chemical handling system includes a chemical storage module, a transport module, and one or more liquid handling modules. The transport module may implement parallel chemical transport, and the system may include a plurality of asynchronously operable liquid handling modules coupled to the parallel transport module.
    Type: Application
    Filed: January 9, 2008
    Publication date: September 18, 2008
    Inventors: Chari Stylli, Samuel S. Beckey, Christopher Bentley Shumate, Peter J. Coassin
  • Patent number: 7383587
    Abstract: A data processing system includes a processor that can operate in a plurality of modes and in either a secure domain or a non-secure domain. At least one secure mode is a mode in the secure domain, and at least one non-secure mode is a mode in the non-secure domain. When the processor is executing a program in a secure mode and that program has access to secure data which is not accessible when the processor is operating in a non-secure mode, the processor is responsive to exception conditions for triggering exception processing. Specifically, the processor is responsive to a parameter specifying which of the exceptions should be handled by a secure mode exception handler executing in a secure mode and which should be handled by an exception handler executing in a mode within a current one of the secure domain and the non-secure domain when that exception occurs.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: June 3, 2008
    Assignee: Arm Limited
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier
  • Patent number: 7325083
    Abstract: In a system supporting more than one operating system, a data processing thread executing on a first operating system may be subject to an interrupt which triggers interrupt handling on a second operating system. When that interrupt handling is completed on the second operating system, the first operating system is resumed using a return interrupt. The return interrupt specifies the data processing thread which is active on the second operating system such that an appropriate task switch or resumption may be made on the first operating system. The technique is particularly well suited to systems utilising a secure operating system and a non-secure operating system executing on the same hardware.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: January 29, 2008
    Assignee: Arm Limited
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Brochier, David Hennah Mansell, Dominic Hugo Symes
  • Patent number: 7305712
    Abstract: There is a provided a data processing system comprising: a processor operable in a plurality of modes and either a secure domain or a non-secure domain including: at least one secure mode being a mode in said secure domain; and at least one non-secure mode being a mode in said non-secure domain; wherein when said processor is executing a program in a secure mode said program has access to secure data which is not accessible when said processor is operating in a non-secure mode; and wherein said processor is responsive to a switching request to initiate a switch between a secure mode and a non-secure mode under control of a mode switching program starting at a location specified by an exception vector associated with said switching request.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: December 4, 2007
    Assignee: ARM Limited
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier
  • Publication number: 20070209414
    Abstract: An adjustable lock assembly that can be used with a sliding window or a sliding door to limit the complete opening of, brace completely shut, or both. The lock assembly can include a first body slidably telescoped with a second body. An affixation device affixes the length of the lock assembly to a selected length. A cuff is disposed around a connection joint defined between the first and second bodies.
    Type: Application
    Filed: March 9, 2007
    Publication date: September 13, 2007
    Inventors: Christopher Bentley, Gerald Majeske
  • Patent number: 7124274
    Abstract: An apparatus for processing data, the apparatus comprising: a processor operable in a plurality of modes and either a secure domain or a non-secure domain including at least one secure mode being a mode in the secure domain; and at least one non-secure mode being a mode in the non-secure domain. When the processor is executing a program in a secure mode, the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. The processor further includes a non-secure translation table base address register and a secure translation table base address register operable in the non-secure and secure domain, respectively, to indicate a region of memory storing either non-secure or secure domain memory mapping data defining how virtual addresses are translated to physical addresses within either the non-secure or secure domain.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: October 17, 2006
    Assignee: Arm Limited
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier, David Hennah Mansell, Michael Robert Nonweiler
  • Patent number: 7117284
    Abstract: A data processing apparatus is operable in a plurality of modes and in either a secure domain or a non-secure domain. When operating in a secure mode within the secure domain a program has access to secure data which is not accessible when the processor is operating in a non-secure mode. A vectored interrupt controller is provided to generate an exception handler address in response to an occurrence of an except condition. The vectored interrupt controller is programmable with parameters specifying for each exception condition whether an exception handler in the secure or the non-secure domain should be triggered and an exception handler address for use if the exception occurs when in the appropriate domain. The vectored interrupt controller also includes a parameter specifying a domain switching exception handler address for use if the exception condition occurs when the processor is not in the appropriate domain.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: October 3, 2006
    Assignee: ARM Limited
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier, David Hennah Mansell, Jonathan Sean Callan
  • Patent number: 7105132
    Abstract: A chemical solution distribution system and method that includes or employs a plurality of liquid handlers where each of the liquid handlers includes a movable table that engages a sample multiwell plate and can align pipettes of the station with different subsets of wells of the multiwell plate where the number of wells of the multiwell plate is a multiple of the number of pipettes of the head of the pipette station. The system further includes and employs four different pumps to enable the system and method to supply four different solutions to wash stations of each of the four liquid handlers.
    Type: Grant
    Filed: February 25, 2002
    Date of Patent: September 12, 2006
    Assignee: Aurora Discovery, Inc.
    Inventors: Christopher Bentley Shumate, Peter J. Coassin
  • Patent number: 7089539
    Abstract: Program instructions in the form of Java bytecodes may be subject to fixed mappings to processing operations or programmable mappings to processing operations. A system is provided with a fixed mapping hardware interpreter, a programmable mapping hardware interpreter and a software interpreter. The fixed mapping hardware interpreter is able to provide high speed interpretation of the common and simple bytecodes. The programmable mapping hardware interpreter is able to provide high speed interpretation of the simple and performance critical programmable bytecodes with the remaining bytecodes and more complicated bytecodes being handled by the software interpreter.
    Type: Grant
    Filed: February 25, 2002
    Date of Patent: August 8, 2006
    Assignee: ARM Limited
    Inventors: Christopher Bentley Dornan, Andrew Christopher Rose