Abstract: An Advanced Emergency Duty Exit Securing Strip having length and elasticity enough to hold open almost any exit device is made of a thin, tough elastomer. A first handle-adaptive hole provides multiple methods to secure a door knob, handle, pushbar, magnetic closure or lever on one side of the door. A constriction slot adjacent the handle-adaptive hole prevents inadvertent loosening of looping methods for securing a door. A latch-enveloping middle portion of the Strip has width and puncture strength enough to cover a door's latch-bolt and strike plate or other latching portion and restrain any spring-bolts or latches from engaging. The remaining handle-adaptive end portion of the Strip wraps around to the far side of the door and secures the far side door mechanisms using one of the multiple methods. Depending on door tolerances, the door will either wedge open or the exit device will be prevented from engaging.

Abstract: A Disposable Emergency Duty Latch Disabling Strip having length and elasticity enough to fit around almost any door jamb security mechanism is made of a thin, tough elastomer. A first handle-adaptive hole fits around a door knob, handle or lever on one side of the door. A latch-enveloping middle portion of the Strip has width and puncture strength enough to cover a door's latch-bolt and strike plate or other latching portion and restrain any spring-bolts or latches from engaging. The remaining handle-adaptive end portion of the Strip wraps around to the far side of the door and is attached to the far side door mechanisms using the remaining handle-adaptive hole. Depending on door tolerances, the door will either wedge open or the lock will be prevented from engaging. The Strip resists heat, cold, shearing, abrasion and can be folded to deploy from a dispenser, belt or pocket.

Abstract: An apparatus includes one or more error-correction decoders, a buffer, and at least one processor. The buffer may be configured to store data to be decoded by the one or more error-correction decoders. The at least one processor is generally enabled to send messages to the one or more error-correction decoders. The messages may contain datapath control information corresponding to data in the buffer to be decoded by the one or more error-correction decoders. The one or more error-correction decoders are generally enabled to decode the data read from the buffer according to the corresponding datapath control information.

Abstract: An apparatus includes one or more error-correction decoders, a buffer, and at least one processor. The buffer may be configured to store data to be decoded by the one or more error-correction decoders. The at least one processor is generally enabled to send messages to the one or more error-correction decoders. The messages may contain datapath control information corresponding to data in the buffer to be decoded by the one or more error-correction decoders. The one or more error-correction decoders are generally enabled to decode the data read from the buffer according to the corresponding datapath control information.

Abstract: An apparatus includes a device interface, a micro-sequencer, and a programmable sequence memory. The device interface may be configured to process a plurality of read/write operations to/from one or more non-volatile memory devices. The micro-sequencer may be configured to communicate with the device interface. The programmable sequence memory is generally readable by the micro-sequencer. In response to the apparatus receiving a command, (a) the micro-sequencer executes a set of instructions starting at a location in the programmable sequence memory according to the command and (b) the micro-sequencer is enabled to perform at least a portion of the command according to a protocol of the one or more non-volatile memory devices, when the one or more non-volatile memory devices are coupled to the device interface.

Abstract: An apparatus includes one or more error-correction decoders, a buffer, at least one direct memory access (DMA) engine, and at least one processor. The buffer may be configured to store data to be decoded by the one or more error-correction decoders. The at least one DMA engine may couple the buffer and the one or more error-correction decoders. The at least one processor may be enabled to send messages to the at least one DMA engine. The messages may be configured to deliver DMA control information and corresponding datapath control information. Data may be read from the buffer based upon the DMA control information and delivered to the one or more error-correction decoders along with the corresponding datapath control information. The one or more error-correction decoders may be enabled to decode the data read from the buffer according to the corresponding datapath control information.

Abstract: An apparatus includes a device interface, a micro-sequencer, and a programmable sequence memory. The device interface may be configured to process a plurality of read/write operations to/from one or more non-volatile memory devices. The micro-sequencer may be configured to communicate with the device interface. The programmable sequence memory is generally readable by the micro-sequencer. In response to the apparatus receiving a command, (a) the micro-sequencer executes a set of instructions starting at a location in the programmable sequence memory according to the command and (b) the micro-sequencer is enabled to perform at least a portion of the command according to a protocol of the one or more non-volatile memory devices, when the one or more non-volatile memory devices are coupled to the device interface.

Abstract: A system includes a control processor, a non-volatile memory device interface, and a micro-sequencer. The control processor may be configured to receive commands and send responses via a command interface. The non-volatile memory device interface may be configured to couple the system to one or more non-volatile memory devices. The micro-sequencer is generally coupled to (i) the control processor and (ii) the non-volatile memory device interface. The micro-sequencer includes a control store readable by the micro-sequencer and writable by the control processor. In response to receiving a particular one of the commands, the control processor is enabled to cause the micro-sequencer to begin executing at a location in the control store according to the particular command and the micro-sequencer is enabled to perform at least a portion of the particular command according to a protocol of the one or more non-volatile memory devices coupled to the non-volatile memory device interface.

Abstract: An apparatus includes one or more error-correction decoders, a buffer, at least one direct memory access (DMA) engine, and at least one processor. The buffer may be configured to store data to be decoded by the one or more error-correction decoders. The at least one DMA engine may couple the buffer and the one or more error-correction decoders. The at least one processor may be enabled to send messages to the at least one DMA engine. The messages may be configured to deliver DMA control information and corresponding datapath control information. Data may be read from the buffer based upon the DMA control information and delivered to the one or more error-correction decoders along with the corresponding datapath control information. The one or more error-correction decoders may be enabled to decode the data read from the buffer according to the corresponding datapath control information.

Abstract: A system includes a control processor, a non-volatile memory device interface, and a micro-sequencer. The control processor may be configured to receive commands and send responses via a command interface. The non-volatile memory device interface may be configured to couple the system to one or more non-volatile memory devices. The micro-sequencer is generally coupled to (i) the control processor and (ii) the non-volatile memory device interface. The micro-sequencer includes a control store readable by the micro-sequencer and writable by the control processor. In response to receiving a particular one of the commands, the control processor is enabled to cause the micro-sequencer to begin executing at a location in the control store according to the particular command and the micro-sequencer is enabled to perform at least a portion of the particular command according to a protocol of the one or more non-volatile memory devices coupled to the non-volatile memory device interface.

Abstract: A method and associated apparatus directed to a piezoelectric micromachined ultrasonic transducer (pMUT) defining an air-backed cavity are provided. A first via defined by a device substrate and associated dielectric layer, and extending to the first electrode, is substantially filled with a first conductive material. A support member engaged with the device substrate defines a second via extending to the first conductive material. The second via has a second conductive material disposed thereon, forms an electrically-conductive engagement with the first conductive material, and extends outwardly of the second via to be accessible externally to the support member.

Abstract: A method and associated apparatus directed to a piezoelectric micromachined ultrasonic transducer (pMUT) defining an air-backed cavity are provided. A first via defined by a device substrate and associated dielectric layer, and extending to the first electrode, is substantially filled with a first conductive material. A support member engaged with the device substrate defines a second via extending to the first conductive material. The second via has a second conductive material disposed thereon, forms an electrically-conductive engagement with the first conductive material, and extends outwardly of the second via to be accessible externally to the support member.

Abstract: A wireless computerized wagering game system comprises a gaming module operable to present a wagering game on which monetary value can be wagered, and a wireless communications module operable to connect the wireless wagering game system to at least one wireless peripheral device. The wireless computerized wagering game is portable, is operable to couple to fixed and portable peripheral devices, and is operable to couple to user-provided and gaming establishment-provided peripherals in various embodiments.