Patents by Inventor Christopher Bueb
Christopher Bueb has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11734195Abstract: A first set of memory access operations is performed at a memory sub-system based on first operation settings that are configured based on a first operating environment of a host system. A detection is made that the host system is operating in a second operating environment that is different from the first operating environment. A level of impact that each operating requirement of a set of operating requirements of the memory sub-system has on a performance of the memory sub-system in view of the second operating environment. A second set of memory access operations is determined based on a respective priority for each operating requirement of the set of operating requirements. A second set of memory access operations is performed at the memory sub-system based on the second set of memory access operation settings.Type: GrantFiled: December 5, 2022Date of Patent: August 22, 2023Assignee: Micron Technology, Inc.Inventors: Christopher Bueb, Poorna Kale
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Publication number: 20230095179Abstract: A first set of memory access operations is performed at a memory sub-system based on first operation settings that are configured based on a first operating environment of a host system. A detection is made that the host system is operating in a second operating environment that is different from the first operating environment. A level of impact that each operating requirement of a set of operating requirements of the memory sub-system has on a performance of the memory sub-system in view of the second operating environment. A second set of memory access operations is determined based on a respective priority for each operating requirement of the set of operating requirements. A second set of memory access operations is performed at the memory sub-system based on the second set of memory access operation settings.Type: ApplicationFiled: December 5, 2022Publication date: March 30, 2023Inventors: Christopher Bueb, Poorna Kale
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Patent number: 11544202Abstract: A priority for each operating requirement of a set of operating requirements of a memory sub-system can be determined. A programming operation setting for a programming operation to be performed at the memory sub-system can be determined based on the priority for each operating requirement. A request to perform the programming operation at the memory sub-system can be received. Responsive to receiving the request to perform the programming operation, the programming operation can be performed at the memory sub-system based on the programming operation setting.Type: GrantFiled: October 21, 2019Date of Patent: January 3, 2023Assignee: Micron Technology, Inc.Inventors: Christopher Bueb, Poorna Kale
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Publication number: 20210117338Abstract: A priority for each operating requirement of a set of operating requirements of a memory sub-system can be determined. A programming operation setting for a programming operation to be performed at the memory sub-system can be determined based on the priority for each operating requirement. A request to perform the programming operation at the memory sub-system can be received. Responsive to receiving the request to perform the programming operation, the programming operation can be performed at the memory sub-system based on the programming operation setting.Type: ApplicationFiled: October 21, 2019Publication date: April 22, 2021Inventors: Christopher Bueb, Poorna Kale
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Patent number: 10741224Abstract: Devices and techniques for NAND cell encoding to improve data integrity are disclosed herein. A high-temperature indicator is obtained and a write operation is received. The write operation is then performed on a NAND cell using a modified encoding in response to the high-temperature indicator. The modified encoding includes a reduced number of voltage distribution positions from an unmodified encoding without changing voltage distribution widths, where each voltage distribution corresponds to a discrete set of states an encoding.Type: GrantFiled: July 22, 2019Date of Patent: August 11, 2020Assignee: Micron Technology, Inc.Inventors: Tyson M. Stichka, Preston Allen Thomson, Scott Anthony Stoller, Christopher Bueb, Jianmin Huang, Kulachet Tanpairoj, Harish Reddy Singidi
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Publication number: 20200058327Abstract: Devices and techniques for NAND cell encoding to improve data integrity are disclosed herein. A high-temperature indicator is obtained and a write operation is received. The write operation is then performed on a NAND cell using a modified encoding in response to the high-temperature indicator. The modified encoding includes a reduced number of voltage distribution positions from an unmodified encoding without changing voltage distribution widths, where each voltage distribution corresponds to a discrete set of states an encoding.Type: ApplicationFiled: July 22, 2019Publication date: February 20, 2020Inventors: Tyson M. Stichka, Preston Allen Thomson, Scott Anthony Stoller, Christopher Bueb, Jianmin Huang, Kulachet Tanpairoj, Harish Reddy Singidi
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Publication number: 20200004446Abstract: Techniques are disclosed, including a method that can include entering a first mode of operation of an apparatus including a memory device, receiving first information indicative of a subsequent download of second information at the memory device, the memory device including a first group of cells configured as multi-level cell (MLC) memory, in response to receipt of the first information, converting a portion of the first group of cells from configuration as MLC memory to configuration as single-level cell (SLC) memory, receiving and storing the second information at the memory device, and upon exiting the first mode of operation, reconfiguring at least a portion of the SLC memory to MLC memory while simultaneously maintaining storage of the second information within the memory device.Type: ApplicationFiled: June 29, 2018Publication date: January 2, 2020Inventors: David Aaron Palmer, Cory J. Reche, Christopher Bueb
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Patent number: 10432230Abstract: Example embodiments described herein may relate error detection and correction on a portion of a codeword in a memory device.Type: GrantFiled: August 5, 2013Date of Patent: October 1, 2019Assignee: Micron Technology, Inc.Inventors: Christopher Bueb, Sean Eilert
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Patent number: 10360947Abstract: Devices and techniques for NAND cell encoding to improve data integrity are disclosed herein. A high-temperature indicator is obtained and a write operation is received. The write operation is then performed on a NAND cell using a modified encoding in response to the high-temperature indicator. The modified encoding includes a reduced number of voltage distribution positions from an unmodified encoding without changing voltage distribution widths, where each voltage distribution corresponds to a discrete set of states an encoding.Type: GrantFiled: August 31, 2017Date of Patent: July 23, 2019Assignee: Micron Technology, Inc.Inventors: Tyson M. Stichka, Preston Thomson, Scott Anthony Stoller, Christopher Bueb, Jianmin Huang, Kulachet Tanpairoj, Harish Singidi
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Publication number: 20190066736Abstract: Devices and techniques for NAND cell encoding to improve data integrity are disclosed herein. A high-temperature indicator is obtained and a write operation is received. The write operation is then performed on a NAND cell using a modified encoding in response to the high-temperature indicator. The modified encoding includes a reduced number of voltage distribution positions from an unmodified encoding without changing voltage distribution widths, where each voltage distribution corresponds to a discrete set of states an encoding.Type: ApplicationFiled: August 31, 2017Publication date: February 28, 2019Inventors: Tyson M. Stichka, Preston Thomson, Scott Anthony Stoller, Christopher Bueb, Jianmin Huang, Kulachet Tanpairoj, Harish Singidi
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Patent number: 10146617Abstract: A method includes calculating a first syndrome of a codeword read from a memory location under a first set of conditions and calculating a second syndrome of the codeword read from the memory location under a second set of conditions. The method also includes analyzing the first and second syndromes and applying one of the first and second syndromes to the codeword to find the codeword having a minimum number of errors.Type: GrantFiled: April 13, 2015Date of Patent: December 4, 2018Assignee: Micron Technology, Inc.Inventors: Christopher Bueb, Sean Eilert
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Patent number: 9563501Abstract: A method includes detecting that a first device in a memory array has degraded, the first device storing a portion of a data record, wherein the data record is encoded using a first error control technique. The method continues with recovering the data record using portions of the data record stored in devices other than the first device in the memory array and encoding the data record using a second error control technique. The method also includes storing the data record in the devices of the memory array other than the first device.Type: GrantFiled: November 30, 2010Date of Patent: February 7, 2017Assignee: Micron Technology, Inc.Inventors: Christopher Bueb, Sean Eilert
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Patent number: 9542121Abstract: A memory device includes a serial interface buffer that receives a hardware-decodable command and an extended interface command. The memory device also includes a logic module that directs the hardware-decodable command to a register for execution by a microcontroller. The logic module additionally loads a command received following the extended interface command into a sub-op-code register, wherein the logic module remains passive after loading the command received following the extended interface command into the sub-op-code register. Also included is a microcontroller that interprets the command in the sub-op-code register.Type: GrantFiled: August 13, 2014Date of Patent: January 10, 2017Assignee: Micron Technology, Inc.Inventors: Christopher Bueb, Poorna Kale, Todd Legler
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Patent number: 9292383Abstract: Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, a plurality of bits may be encoded into a plurality of memory cells by level-shifting a subset of the plurality of multilevel memory cells for a bit of the plurality of bits. Other embodiments may be described and claimed.Type: GrantFiled: October 9, 2014Date of Patent: March 22, 2016Assignee: Micron Technology, Inc.Inventor: Christopher Bueb
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Publication number: 20150220395Abstract: A method includes calculating a first syndrome of a codeword read from a memory location under a first set of conditions and calculating a second syndrome of the codeword read from the memory location under a second set of conditions. The method also includes analyzing the first and second syndromes and applying one of the first and second syndromes to the codeword to find the codeword having a minimum number of errors.Type: ApplicationFiled: April 13, 2015Publication date: August 6, 2015Inventors: CHRISTOPHER BUEB, SEAN EILERT
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Patent number: 9047191Abstract: A method includes calculating a first syndrome of a codeword read from a memory location under a first set of conditions and calculating a second syndrome of the codeword read from the memory location under a second set of conditions. The method also includes analyzing the first and second syndromes and applying one of the first and second syndromes to the codeword to find the codeword having a minimum number of errors.Type: GrantFiled: January 9, 2014Date of Patent: June 2, 2015Assignee: Micron Technology, Inc.Inventors: Christopher Bueb, Sean Eilert
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Publication number: 20150095742Abstract: Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, a plurality of bits may be encoded into a plurality of memory cells by level-shifting a subset of the plurality of multilevel memory cells for a bit of the plurality of bits. Other embodiments may be described and claimed.Type: ApplicationFiled: October 9, 2014Publication date: April 2, 2015Inventor: Christopher Bueb
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Publication number: 20140359169Abstract: A memory device includes a serial interface buffer that receives a hardware-decodable command and an extended interface command. The memory device also includes a logic module that directs the hardware-decodable command to a register for execution by a microcontroller. The logic module additionally loads a command received following the extended interface command into a sub-op-code register, wherein the logic module remains passive after loading the command received following the extended interface command into the sub-op-code register. Also included is a microcontroller that interprets the command in the sub-op-code register.Type: ApplicationFiled: August 13, 2014Publication date: December 4, 2014Inventors: CHRISTOPHER BUEB, POORNA KALE, TODD LEGLER
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Patent number: 8887028Abstract: Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, a plurality of bits may be encoded into a plurality of memory cells by responding to bits of the plurality of bits by changing the logic levels of corresponding groups of memory cells of the plurality of memory cells. Other embodiments may be described and claimed.Type: GrantFiled: February 21, 2014Date of Patent: November 11, 2014Assignee: Micron Technology, Inc.Inventor: Christopher Bueb
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Patent number: 8875006Abstract: Embodiments of the present disclosure provide methods and apparatuses related to NVM devices with extended error correction protection. In some embodiments, a parity cache is used to store parity values of data values stored in a plurality of codewords of an NVM device. Other embodiments may be described and claimed.Type: GrantFiled: July 22, 2013Date of Patent: October 28, 2014Assignee: Micron Technology, Inc.Inventor: Christopher Bueb