Abstract: During operation, an access point may provide a first WLAN and a second WLAN, where the first WLAN uses a WPA2-compatible authentication protocol and the second WLAN uses a WPA3-compatible authentication protocol. In response to an association request or a probe request associated with (or from) an electronic device, the access point may establish a connection with the electronic device using the first WLAN. Then, the access point may confirm, with a computer system, that a binding between a passphrase associated with the electronic device and the second WLAN exists. Alternatively, when the binding does not exist, the access point may establish the binding in the computer system. Next, the access point may perform a BSS transition of the electronic device from the first WLAN to the second WLAN.

Abstract: Aspects of the subject disclosure may include, for example, obtaining first data pertaining to an outage in a first portion of a communications system, obtaining second data pertaining to a relationship between the first portion of the communications system and a second portion of the communications system, analyzing the first data the second data to identify a risk to communication services facilitated by the second portion of the communications system, determining that the risk is greater than a threshold, and generating, based on the determining, a recommendation for reducing the risk. Other embodiments are disclosed.

Abstract: Techniques are disclosed relating to intersection tests for ray tracing in graphics processors. In some embodiments, test circuitry is configured to perform an intersection test based on traversal of an acceleration data structure that includes hierarchically-arranged bounding volumes for a graphics scene, where the test operates on: reduced-precision representations of rays that are quantized versions of initial representations of the rays and reduced-representatives of primitives that are quantized versions of initial representations of the primitives. The test may generate a first result for a first ray and a first primitive that indicates that a line coincident with the first ray definitively intersects the first primitive. The graphics processor may record an intersection for the first ray with the first primitive, based on the first result, without performing an intersection test for the first ray using the initial representation of the first ray and the first primitive.

Abstract: Disclosed techniques relate to forming single-instruction multiple-data (SIMD) groups during ray intersection traversal. In particular, ray intersection circuitry may include dedicated circuitry configured to traverse an acceleration data structure, but may dynamically form a SIMD group to transform ray coordinates when traversing from one level of the data structure to another. This may allow shader processors to execute the SIMD group to perform the transformation. Disclosed techniques may facilitate instancing of graphics models within the acceleration data structure.

Abstract: An energy storing brace to be worn on a limb of a user may include a primary frame and a secondary frame pivotally connected to the primary frame. An energy storage assembly may include a spring member that is spaced apart from the first hinge and the second hinge. A first energized cord path may extend from the first hinge to the energy storage assembly. A tensioning cord may extend from a first anchor section secured relative to the first primary arm, across a first peripheral surface and through the first energized cord path to the spring member. Pivoting the brace from an extended position toward a flexed position may cause (i) the first extension member to exert a tension force on the first cord segment thereby loading the spring member and the spring member applies a restorative spring force to urge the brace to return to the extended position.

Abstract: Techniques are disclosed relating to intersection tests for ray tracing in graphics processors. In some embodiments, test circuitry is configured to perform intersection tests that operate on reduced-precision representations of rays that were generated by quantizing initial representations of the rays and reduced-precision representations of primitives that were generated by quantizing initial representations of the primitives. Some reduced-precision tests (e.g., for any-hit rays) may generate a definitive hit according to the initial representations. In this situation, graphics processing circuitry may record an intersection with the reduced-precision representation of the primitive for the ray based on the first result, without performing an intersection test for the first ray using the initial representation of the ray and the primitive. Disclosed techniques may advantageously reduce power consumption, improve performance, or both.

Abstract: Techniques are disclosed relating to operand routing among SIMD pipelines. In some embodiments, an apparatus includes a set of multiple hardware pipelines configured to execute a single-instruction multiple-data (SIMD) instruction for multiple threads in parallel, wherein the instruction specifies first and second architectural registers. In some embodiments, the pipelines include execution circuitry configured to perform operations using one or more pipeline stages of the pipeline. In some embodiments, the pipelines include routing circuitry configured to select, based on the instruction, a first input operand for the execution circuitry from among: a value from the first architectural register from thread-specific storage for another pipeline and a value from the second architectural register from thread-specific storage for a thread assigned to another pipeline.

Abstract: Additive mixtures for nonaqueous battery electrolytes have been discovered that provide for improved performance, and particularly for improved lifetime (cycle life and stability) in high voltage, rechargeable lithium ion batteries. The battery electrolytes comprise less than 10% by weight of an additive mixture comprising an additive solvent, a sulfur containing compound, and lithium difluorophosphate.

Abstract: Techniques are disclosed relating to primitive intersection testing for ray tracing in graphics processors. In some embodiments, a graphics processor includes ray intersection circuitry configured to perform an intersection test, which includes to: quantize a first representation of the primitive to generate a reduced-precision interval representation of the primitive, quantize a first representation of the ray to generate a reduced-precision interval representation of the ray, and determine, using interval arithmetic, an initial intersection result based on coordinates of the interval representation of the primitive and coordinates of the interval representation of the ray. The initial intersection result may be a conservative result such that a miss indicated by the initial intersection result is guaranteed not to be a hit for the first representation of the primitive and first representation of the ray.

Abstract: Techniques are disclosed relating to ray intersection in the context of motion blur. In some embodiments, a graphics processor includes time-oblivious ray intersect circuitry configured to receive coordinates for a ray and traverse a bounding volume hierarchy (BVH) data structure based on the coordinates to determine whether the ray intersects with one or more bounding regions of a graphics space. In some embodiments, in response to reaching a temporal branch element of the BVH data structure, the ray intersect circuitry initiates a shader program that determines a sub-tree of the BVH data structure for further traversal by the ray intersection circuitry, where the sub-tree corresponds to a portion of a motion-blur interval in which the ray falls. This may provide accurate ray tracing for motion blur while reducing area and power consumption of intersect circuitry, relative to time-aware implementations.

Abstract: Techniques are disclosed relating to operand routing among SIMD pipelines. In some embodiments, an apparatus includes a set of multiple hardware pipelines configured to execute a single-instruction multiple-data (SIMD) instruction for multiple threads in parallel, wherein the instruction specifies first and second architectural registers. In some embodiments, the pipelines include execution circuitry configured to perform operations using one or more pipeline stages of the pipeline. In some embodiments, the pipelines include routing circuitry configured to select, based on the instruction, a first input operand for the execution circuitry from among: a value from the first architectural register from thread-specific storage for another pipeline and a value from the second architectural register from thread-specific storage for a thread assigned to another pipeline.

Abstract: Techniques are disclosed relating to intersection tests for ray tracing in graphics processors. In some embodiments, test circuitry is configured to perform intersection tests that operate on reduced-precision representations of rays that were generated by quantizing initial representations of the rays and reduced-precision representations of primitives that were generated by quantizing initial representations of the primitives. Some reduced-precision tests (e.g., for any-hit rays) may generate a definitive hit according to the initial representations. In this situation, graphics processing circuitry may record an intersection with the reduced-precision representation of the primitive for the ray based on the first result, without performing an intersection test for the first ray using the initial representation of the ray and the primitive. Disclosed techniques may advantageously reduce power consumption, improve performance, or both.

Abstract: Techniques are disclosed relating to primitive intersection testing for ray tracing in graphics processors. In some embodiments, a graphics processor includes ray intersection circuitry configured to perform an intersection test, which includes to: quantize a first representation of the primitive to generate a reduced-precision interval representation of the primitive, quantize a first representation of the ray to generate a reduced-precision interval representation of the ray, and determine, using interval arithmetic, an initial intersection result based on coordinates of the interval representation of the primitive and coordinates of the interval representation of the ray. The initial intersection result may be a conservative result such that a miss indicated by the initial intersection result is guaranteed not to be a hit for the first representation of the primitive and first representation of the ray.

Abstract: Disclosed techniques relate to acceleration data structure for ray intersection testing. In some embodiments, storage circuitry stores node data for a spatially organized acceleration data structure, including to store the following node information for a given node: origin coordinates for the node and, for a given child node of multiple child nodes, child information that includes: quantized bounding region information for a bounding region corresponding to the child node, where the quantized bounding region information encodes bounding region coordinates as offsets relative to the origin coordinates. Traversal circuitry may traverse multiple nodes of the data structure and determine whether a ray intersects a bounding region indicated by given a node of the data structure based on the node information. Disclosed techniques may provide substantial improvements to performance, data size, and power consumption.

Abstract: Disclosed are various examples for enrolling a device in a management service. An enrollment wizard can include a series of user interfaces to facilitate enrollment of a device in the management service. Enrollment data can be obtained from the user and sent to the management service for authentication of the user and device. A user interface object can be instantiated to access a webpage within a user interface of the enrollment wizard for downloading a configuration profile provided by the management service. A user can be redirected to a settings application to install the configuration profile.

Abstract: The present invention is directed to the tartrate salt of a FAK inhibitor defined by formula (I) below, and the use of that inhibitor for treating a proliferative disease.

Abstract: Methods, and system, and entertainment device are provided for identifying a user. A method includes detecting acceleration of a user manipulated component, comparing the detected acceleration with user acceleration that is associated with a user of the electronic device, identifying the user of the electronic device based on the comparison of the detected acceleration and the user acceleration, and operating the electronic device based on the identified user of the electronic device.

Abstract: Techniques are disclosed relating to ray intersection in the context of motion blur. In some embodiments, a graphics processor includes time-oblivious ray intersect circuitry configured to receive coordinates for a ray and traverse a bounding volume hierarchy (BVH) data structure based on the coordinates to determine whether the ray intersects with one or more bounding regions of a graphics space. In some embodiments, in response to reaching a temporal branch element of the BVH data structure, the ray intersect circuitry initiates a shader program that determines a sub-tree of the BVH data structure for further traversal by the ray intersection circuitry, where the sub-tree corresponds to a portion of a motion-blur interval in which the ray falls. This may provide accurate ray tracing for motion blur while reducing area and power consumption of intersect circuitry, relative to time-aware implementations.

Abstract: Disclosed techniques relate to primitive testing associated with ray intersection processing for ray tracing. In some embodiments, shader circuitry executes a first SIMD group that includes a ray intersect instruction for a set of rays. Ray intersect circuitry traverses, in response to the ray intersect instruction, multiple nodes in a spatially organized acceleration data structure (ADS). In response to reaching a node of the ADS that indicates one or more primitives, the apparatus forms a second SIMD group that executes one or more instructions to determine whether a set of rays that have reached the node intersect the one or more primitives. The shader circuitry may execute the first SIMD group to shade one or more primitives that are indicated as intersected based on results of execution of the second SIMD group. Thus, disclosed techniques may use both dedicated ray intersect circuitry and dynamically formed SIMD groups executed by shader processors to detect ray intersection.

Abstract: Techniques are disclosed relating to testing whether a ray intersects a graphics primitive, e.g., for ray tracing. In some embodiments, intersection circuitry performs a reduced-precision conservative intersection test and shader circuitry performs an original-precision intersection test if the intersection circuitry indicates a hit. The intersection circuitry may quantize the ray (and may quantize the primitive or may receive a quantized representation of the primitive) and generates a potential error value based on propagation of quantization error for the primitive and ray. The intersection circuitry then determines an intersection result for the reduced-precision test based on the quantized primitive data and the potential error. In various embodiments, disclosed techniques may improve performance or reduce power consumption by reducing the number of original-precision intersection tests that do not result in hits.