Abstract: Semiconductor wafer alignment processes are described. In one embodiment, a first geometric shape is formed over a substrate and has a plurality of sides. A majority of the sides are formed along lines which intersect with another side's line at angles greater than 90.degree.. A second geometric shape is formed over the first geometric shape and is substantially the same as, but different in dimension from the first geometric shape. The position of the shapes is inspected relative to one another to ascertain whether the shapes are misaligned. In another embodiment, an enclosed polygon is formed over the substrate and each of the polygon's sides is joined with another of the polygon's sides to define an angle greater than 90.degree.. A shape is provided elevationally displaced from and received entirely inside the polygon when viewed from over the substrate. The relative positions of the polygon and the elevationally displaced shape are inspected for alignment.