Abstract: A multiple operating-mode comparator system can be useful for high bandwidth and low power automated testing. The system can include a gain stage configured to drive a high impedance input of a comparator output stage, wherein the gain stage includes a differential switching stage coupled to an adjustable impedance circuit, and an impedance magnitude characteristic of the adjustable impedance circuit corresponds to a bandwidth characteristic of the gain stage. The comparator output stage can include a buffer circuit coupled to a low impedance comparator output node. The buffer circuit can provide a reference voltage for a switched output signal at the output node in a higher speed mode, and the buffer circuit can provide the switched output signal at the output node in a lower power mode.

Abstract: A test system can receive a test signal from a device under test (DUI) via a first signal path. A comparator circuit can receive the test signal and, in response, generate an intermediate output signal based on a magnitude relationship between the test signal a comparator reference signal. A compensation circuit can generate a correction signal that is complementary to a portion of the received test signal, such as to correct for loading effects of the first signal path. The test system can include an output circuit configured to provide a corrected differential output signal that is based on a combination of the intermediate output signal and the correction signal.

Abstract: A multiple operating-mode comparator system can be useful for high bandwidth and low power automated testing. The system can include a gain stage configured to drive a high impedance input of a comparator output stage, wherein the gain stage includes a differential switching stage coupled to an adjustable impedance circuit, and an impedance magnitude characteristic of the adjustable impedance circuit corresponds to a bandwidth characteristic of the gain stage. The comparator output stage can include a buffer circuit coupled to a low impedance comparator output node. The buffer circuit can provide a reference voltage for a switched output signal at the output node in a higher speed mode, and the buffer circuit can provide the switched output signal at the output node in a lower power mode.

Abstract: A force-sense system for providing signals to, or receiving signals from, a device under test (DUT) at a first DUT node. The system can include an interface coupling first and second portions of a first force-sense measurement device, such as a parametric measurement unit. The first and second portions of the first force-sense measurement device can be provided using respective different integrated circuits, such as can comprise different semiconductor dies of different die types. In a first test mode, the interface can be configured to communicate a first DUT force signal from the first portion to the second portion of the first force-sense measurement device, and in a second test mode the interface can be configured to communicate DUT sense information, received from the DUT at the first DUT node, from the second portion to the first portion of the first force-sense measurement device.

Abstract: A force-sense system can provide signals to, or receive signals from, a device under test (DUT) at a first DUT node. The system can include output buffer circuitry configured to provide a DUT signal to the DUT in response to a force control signal at a buffer control node, and controller circuitry configured to provide the force control signal at the buffer control node. The system can include bypass circuitry configured to selectively bypass the controller circuitry and provide an auxiliary control signal at the buffer control node. The auxiliary control signal can be used for system calibration. In an example, an external calibration circuit can provide the auxiliary control signal in response to information received from the DUT.

Abstract: In a test system that provides a high fidelity output signal, a transition driving circuit can selectively enable multiple, parallel current paths based on a desired voltage transition. The transition driving circuit can include a first switch configured to switch a first current path between an output node and a first current source/sink, and a second switch configured to switch a second current path between the output node and the first current source/sink. The transition driving circuit can include a control circuit that is configured to receive information about a desired voltage transition and, depending on a magnitude of the desired voltage transition, to selectively turn on one or both of the first and second switches to enable one or both of the first and second current paths to provide respective portions of the output signal from the first current source/sink to the output node of the test system.

Abstract: A force-sense system for providing signals to, or receiving signals from, a device under test (DUT) at a first DUT node. The system can include an interface coupling first and second portions of a first force-sense measurement device, such as a parametric measurement unit. The first and second portions of the first force-sense measurement device can be provided using respective different integrated circuits, such as can comprise different semiconductor dies of different die types. In a first test mode, the interface can be configured to communicate a first DUT force signal from the first portion to the second portion of the first force-sense measurement device, and in a second test mode the interface can be configured to communicate DUT sense information, received from the DUT at the first DUT node, from the second portion to the first portion of the first force-sense measurement device.

Abstract: A force-sense system can provide signals to, or receive signals from, a device under test (DUT) at a first DUT node. The system can include output buffer circuitry configured to provide a DUT signal to the DUT in response to a force control signal at a buffer control node, and controller circuitry configured to provide the force control signal at the buffer control node. The system can include bypass circuitry configured to selectively bypass the controller circuitry and provide an auxiliary control signal at the buffer control node. The auxiliary control signal can be used for system calibration. In an example, an external calibration circuit can provide the auxiliary control signal in response to information received from the DUT.

Abstract: A pin driver control system for enhancing pulse fidelity can include a first current switch circuit with a current input node and a voltage input node, wherein the first current switch circuit provides a switched output current signal in response to a voltage control signal at the voltage input node. The system can further include a first current source configured to receive a bias control signal and, in response, provide a drive current signal to the current input node of the first current switch. The drive current signal can have a magnitude that exceeds a magnitude of the switched output current signal. The system can further include a bias control circuit configured to receive information about a desired bias current magnitude for use by the first current switch circuit and, in response, provide the bias control signal to the first current source.

Abstract: A multiple operating-mode comparator system can be useful for high bandwidth and low power automated testing. The system can include a gain stage configured to drive a high impedance input of a comparator output stage, wherein the gain stage includes a differential switching stage coupled to an adjustable impedance circuit, and an impedance magnitude characteristic of the adjustable impedance circuit corresponds to a bandwidth characteristic of the gain stage. The comparator output stage can include a buffer circuit coupled to a low impedance comparator output node. The buffer circuit can provide a reference voltage for a switched output signal at the output node in a higher speed mode, and the buffer circuit can provide the switched output signal at the output node in a lower power mode.

Abstract: A multiple operating-mode comparator system can be useful for high bandwidth and low power automated testing. The system can include a gain stage configured to drive a high impedance input of a comparator output stage, wherein the gain stage includes a differential switching stage coupled to an adjustable impedance circuit, and an impedance magnitude characteristic of the adjustable impedance circuit corresponds to a bandwidth characteristic of the gain stage. The comparator output stage can include a buffer circuit coupled to a low impedance comparator output node. The buffer circuit can provide a reference voltage for a switched output signal at the output node in a higher speed mode, and the buffer circuit can provide the switched output signal at the output node in a lower power mode.

Abstract: A test system can use first and different second driver stages to provide test signals to a device under test (DUT). A compound stage can receive signals from the driver stages and provide a voltage output signal to the DUT, such as via a gain circuit. The compound stage can include a buffer circuit configured to provide a first portion of the voltage output signal based on a first output signal from the first driver stage, and the compound stage can include a transimpedance circuit configured to provide a second portion of the voltage output signal based on a second output signal from the second driver stage. In an example, the gain circuit can receive a superposition signal comprising the first and second portions of the voltage output signal and, in response, provide a test signal to the DUT.

Abstract: A multiple operating-mode comparator system can be useful for high bandwidth and low power automated testing. The system can include a gain stage configured to drive a high impedance input of a comparator output stage, wherein the gain stage includes a differential switching stage coupled to an adjustable impedance circuit, and an impedance magnitude characteristic of the adjustable impedance circuit corresponds to a bandwidth characteristic of the gain stage. The comparator output stage can include a buffer circuit coupled to a low impedance comparator output node. The buffer circuit can provide a reference voltage for a switched output signal at the output node in a higher speed mode, and the buffer circuit can provide the switched output signal at the output node in a lower power mode.

Abstract: A stabilization technique is disclosed that suppresses or inhibits glitching behavior on automated test equipment (ATE) during mode transitions. Adjustable stabilizing circuitry can be coupled to at least one of a force voltage circuit or a force current circuit is forcing voltage or current to a device under test (DUT). The adjustable stabilizing circuitry can be adjustably configurable in response to whether at least one of a current clamp or a voltage clamp is in an active clamping mode. In this manner, unwanted glitching behavior associated with mode changes can be reduced or suppressed.

Abstract: A pin driver control system for enhancing pulse fidelity can include a first current switch circuit with a current input node and a voltage input node, wherein the first current switch circuit provides a switched output current signal in response to a voltage control signal at the voltage input node. The system can further include a first current source configured to receive a bias control signal and, in response, provide a drive current signal to the current input node of the first current switch. The drive current signal can have a magnitude that exceeds a magnitude of the switched output current signal. The system can further include a bias control circuit configured to receive information about a desired bias current magnitude for use by the first current switch circuit and, in response, provide the bias control signal to the first current source.

Abstract: A stabilization technique is disclosed that suppresses or inhibits glitching behavior on automated test equipment (ATE) during mode transitions. Adjustable stabilizing circuitry can be coupled to at least one of a force voltage circuit or a force current circuit is forcing voltage or current to a device under test (DUT). The adjustable stabilizing circuitry can be adjustably configurable in response to whether at least one of a current clamp or a voltage clamp is in an active clamping mode. In this manner, unwanted glitching behavior associated with mode changes can be reduced or suppressed.

Abstract: A test system can use first and different second driver stages to provide test signals to a device under test (DUT). A compound stage can receive signals from the driver stages and provide a voltage output signal to the DUT, such as via a gain circuit. The compound stage can include a buffer circuit configured to provide a first portion of the voltage output signal based on a first output signal from the first driver stage, and the compound stage can include a transimpedance circuit configured to provide a second portion of the voltage output signal based on a second output signal from the second driver stage. In an example, the gain circuit can receive a superposition signal comprising the first and second portions of the voltage output signal and, in response, provide a test signal to the DUT.

Abstract: This disclosure is in the field of electronics and more specifically in the field of timing control electronics. In an example, a timing control system can include or use an array of circuit cells, and each cell can provide a signal delay using a fixed delay or interpolation. The interpolation can include, in one or more cells, using three timing signals with substantially different delays to create a delayed output signal. Linearity of the delayed output signal is thereby improved. In an example, an impedance transformation circuit can be applied to improve a bandwidth in one or more of the cells to thereby improve the bandwidth of the timing control system.

Abstract: A multiple-level driver circuit, such as for providing several different signals to a device under test (DUT) in an automated test system, can include multiple diode bridge circuits. In an example, a first diode bridge circuit is configured to receive a multiple-valued input voltage signal, having at least two different DC voltage signal levels, at an input node and, in response, to selectively provide a corresponding multiple-valued output voltage signal at an output node. The first diode bridge circuit can operate in a conducting and non-commutated state when it is used to selectively provide the multiple-valued output voltage signal at the output node.

Abstract: This disclosure is in the field of electronics and more specifically in the field of timing control electronics. In an example, a timing control system can include or use an array of circuit cells, and each cell can provide a signal delay using a fixed delay or interpolation. The interpolation can include, in one or more cells, using three timing signals with substantially different delays to create a delayed output signal. Linearity of the delayed output signal is thereby improved. In an example, an impedance transformation circuit can be applied to improve a bandwidth in one or more of the cells to thereby improve the bandwidth of the timing control system.