Abstract: Multi-layer configurable timing switch fabrics and related methods are disclosed for selectively distributing multiple timing sources to multiple timing consumers. Configurable timing switches are used at central and multiple local levels within the housing for a network-connected processing system to selectively distribute the timing sources to the timing consumers. As such, significant flexibility is provided with respect to what timing sources can be received within the system and how these timing sources are distributed to different timing consumers. Further, timing information can be generated within the network-connected processing system based upon network communications received from timing consumers, and this generated timing information can also be used as timing sources for the multi-layer configurable timing switch fabric.

Abstract: Power entry and distribution for network communication systems are disclosed. For certain embodiments depicted, a power distribution board with an open-grid configuration receives power feed/return lines from a power entry connector and distributes the power feed/return lines for a network processing system. The open-grid configuration facilitates airflow through a chassis and thereby provides improved cooling. Further, a modular power entry connector can be used to facilitate connection of power feed/return cables to the chassis for the network processing systems while improving safety for high power implementations.

Abstract: Multi-layer configurable timing switch fabrics and related methods are disclosed for selectively distributing multiple timing sources to multiple timing consumers. Configurable timing switches are used at central and multiple local levels within the housing for a network-connected processing system to selectively distribute the timing sources to the timing consumers. As such, significant flexibility is provided with respect to what timing sources can be received within the system and how these timing sources are distributed to different timing consumers. Further, timing information can be generated within the network-connected processing system based upon network communications received from timing consumers, and this generated timing information can also be used as timing sources for the multi-layer configurable timing switch fabric.

Abstract: Power entry and distribution for network communication systems are disclosed. For certain embodiments depicted, a power distribution board with an open-grid configuration receives power feed/return lines from a power entry connector and distributes the power feed/return lines for a network processing system. The open-grid configuration facilitates airflow through a chassis and thereby provides improved cooling. Further, a modular power entry connector can be used to facilitate connection of power feed/return cables to the chassis for the network processing systems while improving safety for high power implementations.

Abstract: Air filter and cable management assemblies for network communication systems are disclosed. The assemblies include filters that cover one or more communication line cards and their associated connection panels. The assemblies also include cable support structures with cable support brackets that support connected cables while restricting airflow so that airflow is forced through the filter towards the connection panels. This airflow can then pass into housings for the line cards and other circuitry, such as fabric cards, to provide desired cooling. Fan subsystems can also be provided to facilitate airflow. Advantageously, the disclosed air filter and cable management assemblies allow for filtered cooling of stacked network communication systems while greatly simplifying the complexity of the filter and cable installation and maintenance.

Abstract: Systems and methods are disclosed for playback of detected timing events with detected phase variations. Disclosed signal generation embodiments can be used to generate digital signals having desired phase variation. Disclosed event detection circuitry can be used to generate event timing data representing one or more phase variations in detected events. The disclosed signal generation embodiments can utilize the event timing data to playback detect events along with the measured phase variations. Further, the signal generation circuitry and the event detection circuitry can be implemented in different devices or can be implemented in the same device.

Abstract: Systems and methods are disclosed for precise event time measurement. High speed serializer and deserializer circuitry are combined with high speed logic elements, such as exclusive-OR (XOR) or exclusive-not-OR (XNOR) logic circuitry, to achieve a measurement precision based upon a bit period associated with the high speed circuitry rather than upon slower reference clock signals. In certain embodiments, the disclosed systems and methods generate digital signal patterns, serialize them, transmit them as a high speed bit stream, utilize an event occurrence signal and logic circuitry to produce a modified bit stream, deserialize the modified bit stream to produce a modified digital signal pattern, compare the modified signal pattern with a predicted signal pattern, and determine bit positions or bit periods at which events occur based upon this comparison. These bit positions can then be used to generate precise timestamps and related time information for detected events.

Abstract: Systems and methods are disclosed for precise event time measurement using high-speed deserializer circuitry. The described embodiments utilize high speed deserializer circuitry to achieve a precision based upon a bit period associated with the operation of the high speed operation of the deserializer circuitry rather than upon slower speed clock periods associated with reference clock signals. In certain embodiments, the disclosed systems and methods receive an event occurrence signal and use deserializer circuitry to sample the event occurrence signal and to produce multi-bit parallel data representing the event occurrence signal. Precise timestamps can then be generated based upon the multi-bit parallel data. Advantageously, the precision of these time measurements is associated with the bit period of the high speed operation of the deserializer circuitry and are not limited to lower speeds at which other circuitry within the system may be operating, for example, based upon a slower reference clock signal.

Abstract: Systems and methods are disclosed for precise event time measurement using high-speed deserializer circuitry. The described embodiments utilize high speed deserializer circuitry to achieve a precision based upon a bit period associated with the operation of the high speed operation of the deserializer circuitry rather than upon slower speed clock periods associated with reference clock signals. In certain embodiments, the disclosed systems and methods receive an event occurrence signal and use deserializer circuitry to sample the event occurrence signal and to produce multi-bit parallel data representing the event occurrence signal. Precise timestamps can then be generated based upon the multi-bit parallel data. Advantageously, the precision of these time measurements is associated with the bit period of the high speed operation of the deserializer circuitry and are not limited to lower speeds at which other circuitry within the system may be operating, for example, based upon a slower reference clock signal.

Abstract: Systems and methods are disclosed for precise event time measurement. High speed serializer and deserializer circuitry are combined with high speed logic elements, such as exclusive-OR (XOR) or exclusive-not-OR (XNOR) logic circuitry, to achieve a measurement precision based upon a bit period associated with the high speed circuitry rather than upon slower reference clock signals. In certain embodiments, the disclosed systems and methods generate digital signal patterns, serialize them, transmit them as a high speed bit stream, utilize an event occurrence signal and logic circuitry to produce a modified bit stream, deserialize the modified bit stream to produce a modified digital signal pattern, compare the modified signal pattern with a predicted signal pattern, and determine bit positions or bit periods at which events occur based upon this comparison. These bit positions can then be used to generate precise timestamps and related time information for detected events.

Abstract: Systems and methods are disclosed for playback of detected timing events with detected phase variations. Disclosed signal generation embodiments can be used to generate digital signals having desired phase variation. Disclosed event detection circuitry can be used to generate event timing data representing one or more phase variations in detected events. The disclosed signal generation embodiments can utilize the event timing data to playback detect events along with the measured phase variations. Further, the signal generation circuitry and the event detection circuitry can be implemented in different devices or can be implemented in the same device.

Abstract: An optical line interface assembly for insertion in a slot of a communications equipment rack includes a board having serial interfaces formed to couple to optical interface modules. The interface assembly also includes optical interface modules removably coupled to the serial interfaces to permit replacement of selected optical interface modules while the remaining optical interface modules remain coupled to optical signal lines.

Abstract: A method for training a modem includes selecting a transmission rate from one of a plurality of bauds, each baud identifying at least one transmission rate. The method also includes attempting to train the modem at the transmission rate and measuring the signal quality after the modem trains. The method further includes accessing a table of acceptable signal qualities, the table corresponding to the baud of the first transmission rate. In addition, the method includes comparing the measured signal quality to at least one acceptable signal quality identified by a provisioned margin in the table to determine if the measured signal quality is acceptable.

Abstract: An apparatus for generating a precision frequency includes a receiver that tracks a CDMA pilot signal and extracts frequency and phase information. This information is then used by a processor to control a precision oscillator. The precision oscillator generates a precise frequency based on the CDMA pilot signal. Time of day information is also extracted by the receiver and processor.

Abstract: An apparatus for generating a precision frequency includes a receiver that tracks a CDMA pilot signal and extracts frequency and phase information. This information is then used by a processor to control a precision oscillator. The precision oscillator generates a precise frequency based on the CDMA pilot signal. Time of day information is also extracted by the receiver and processor.