Patents by Inventor Christopher Catano
Christopher Catano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20260130145Abstract: A method includes providing a structure in a chamber, wherein the structure comprising a first layer disposed over a substrate and a second layer disposed over the first layer; forming a mask over the structure, wherein the mask includes a plurality of protruding structures defining a plurality of openings, respectively; etching, through the mask, one or more portions of the second layer using a first gas to expose one or more portions of the first layer; based on a second gas, forming a plurality of cap structures covering upper portions of the protruding structures, respectively, and etching, through the mask with the cap structures, the one or more exposed portions of the first layer; and etching, through the mask, one or more portions of another second layer disposed below the first layer using the first gas.Type: ApplicationFiled: November 7, 2024Publication date: May 7, 2026Applicant: Tokyo Electron LimitedInventor: Christopher CATANO
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Publication number: 20260033264Abstract: A method includes providing a structure in a chamber, wherein the structure comprising a plurality of first layers and a plurality of second layers alternately stacked on top of one another; exposing the structure to a first gas, thereby removing one or more portions of a topmost one of the plurality of second layers that was intact through a mask; exposing the structure to a second gas, thereby converting one or more portions of a topmost one of the plurality of first layers that was intact; and exposing the structure to the first gas, thereby removing the one or more converted portions of the topmost first layer.Type: ApplicationFiled: July 23, 2024Publication date: January 29, 2026Inventors: Christopher CATANO, Scott LEFEVRE, Jeffrey SHEARER
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Publication number: 20250308988Abstract: A method for making a semiconductor device can include providing an intermediate structure comprising a substrate, a metal layer, a graphene layer, and a mask layer, where the metal layer is over the substrate, where the graphene layer is over the metal layer, where the mask layer is over the graphene layer, and where the mask layer and the graphene layer are patterned and etched with recesses opening to a top surface of the metal layer such that sidewalls of the graphene layer are exposed in the recesses, conformally depositing a barrier layer over the intermediate structure such that the barrier layer covers the sidewalls of the graphene layer in the recesses, and anisotropically etching the metal layer via the recesses.Type: ApplicationFiled: March 28, 2024Publication date: October 2, 2025Inventors: Christopher Catano, Na Young Bae, Jeffrey Shearer, Brandon Byrns, Joshua Larose, Nicholas Joy, David L O’Meara
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Publication number: 20250210374Abstract: A method for fabricating semiconductor devices is disclosed. The method includes sequentially forming at least a first hardmask layer and a second hardmask layer over a metallic layer. The method includes patterning the second hardmask layer and then the first hardmask layer. The method includes oxidizing a sidewall of the patterned first hardmask layer. The method includes removing the oxidized sidewall of the first hardmask layer. The method includes etching the metallic layer using a remaining portion of the first hardmask layer as a mask.Type: ApplicationFiled: December 20, 2023Publication date: June 26, 2025Applicant: Tokyo Electron LimitedInventors: Christopher CATANO, Brandon BYRNS, Matthew REDNOR, Jeffrey SHEARER
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Publication number: 20240379372Abstract: A method for forming a semiconductor device can include providing a substrate having a patterned structure comprising semiconductor materials, where the patterned structure has a side profile including indentations, such as a patterned film stack, and where a spacer layer is conformally deposited over the patterned structure and within the indentations, reacting a surface of the spacer layer with a plasma-excited first etch gas to form a reacted layer on the spacer layer, wherein the plasma-excited first etch gas includes fluorine, hydrogen, and nitrogen, and removing at least part of the reacted layer by ion bombardment from exposure to a plasma-excited second etch gas. The spacer layer can be SiOCN. The reacted layer can be ammonium fluorosilicate. The first etch gas can contain SF6, H2, and N2, or NF3, H2, and N2. The reacting and removing can be done at room temperature in a same chamber.Type: ApplicationFiled: March 28, 2024Publication date: November 14, 2024Inventors: Adam Pranda, Christopher Catano, Yusuke Lent-Yoshida, Aelan Mosden, Yun Han, Ken Kobayashi
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Patent number: 12009430Abstract: Residue at the base of a feature in a substrate to be etched is limited so that improved profiles may be obtained when forming vertical, narrow pitch, high aspect ratio features, for example fin field effect transistor (FinFET) gates. A thin bottom layer of the feature is formed of a different material than the main layer of the feature. The bottom material may be comprised of a material that preferentially etches and/or preferentially oxidizes as compared to the main layer. The bottom layer may comprise silicon germanium. The preferential etching characteristics may provide a process in which un-etched residuals do not remain. Even if residuals remain, after etch of the feature, an oxidation process may be performed. Enhanced oxidation rates of the bottom material allow any remaining residual to be oxidized. Plasma oxidation may be used. The oxidized material may then be removed by utilizing standard oxide removal mechanisms.Type: GrantFiled: February 5, 2020Date of Patent: June 11, 2024Assignee: Tokyo Electron LimitedInventors: Sergey Voronin, Christopher Catano, Sang Cheol Han, Shyam Sridhar, Yusuke Yoshida, Christopher Talone, Alok Ranjan
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Patent number: 11837467Abstract: In certain embodiments, a method of processing a semiconductor substrate includes positioning a semiconductor substrate in a plasma chamber of a plasma tool. The semiconductor substrate includes a film stack that includes silicon layers and germanium-containing layers in an alternating stacked arrangement, with at least two silicon layers and at least two germanium-containing layers. The method includes exposing, in a first plasma step executed in the plasma chamber, the film stack to a first plasma. The first plasma is generated from first gases that include nitrogen gas, hydrogen gas, and fluorine gas. The method includes exposing, in a second plasma step executed in the plasma chamber, the film stack to a second plasma. The second plasma is generated from second gases comprising fluorine gas and oxygen gas. The second plasma selectively etches the silicon layers.Type: GrantFiled: July 12, 2022Date of Patent: December 5, 2023Assignee: Toyko Electron LimitedInventors: Pingshan Luan, Christopher Catano, Aelan Mosden
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Publication number: 20220351970Abstract: In certain embodiments, a method of processing a semiconductor substrate includes positioning a semiconductor substrate in a plasma chamber of a plasma tool. The semiconductor substrate includes a film stack that includes silicon layers and germanium-containing layers in an alternating stacked arrangement, with at least two silicon layers and at least two germanium-containing layers. The method includes exposing, in a first plasma step executed in the plasma chamber, the film stack to a first plasma. The first plasma is generated from first gases that include nitrogen gas, hydrogen gas, and fluorine gas. The method includes exposing, in a second plasma step executed in the plasma chamber, the film stack to a second plasma. The second plasma is generated from second gases comprising fluorine gas and oxygen gas. The second plasma selectively etches the silicon layers.Type: ApplicationFiled: July 12, 2022Publication date: November 3, 2022Inventors: Pingshan Luan, Christopher Catano, Aelan Mosden
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Patent number: 11424120Abstract: In certain embodiments, a method of processing a semiconductor substrate includes positioning a semiconductor substrate in a plasma chamber of a plasma tool. The semiconductor substrate includes a film stack that includes silicon layers and germanium-containing layers in an alternating stacked arrangement, with at least two silicon layers and at least two germanium-containing layers. The method includes exposing, in a first plasma step executed in the plasma chamber, the film stack to a first plasma. The first plasma is generated from first gases that include nitrogen gas, hydrogen gas, and fluorine gas. The method includes exposing, in a second plasma step executed in the plasma chamber, the film stack to a second plasma. The second plasma is generated from second gases comprising fluorine gas and oxygen gas. The second plasma selectively etches the silicon layers.Type: GrantFiled: January 22, 2021Date of Patent: August 23, 2022Assignee: Tokyo Electron LimitedInventors: Pingshan Luan, Christopher Catano, Aelan Mosden
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Publication number: 20220238309Abstract: In certain embodiments, a method of processing a semiconductor substrate includes positioning a semiconductor substrate in a plasma chamber of a plasma tool. The semiconductor substrate includes a film stack that includes silicon layers and germanium-containing layers in an alternating stacked arrangement, with at least two silicon layers and at least two germanium-containing layers. The method includes exposing, in a first plasma step executed in the plasma chamber, the film stack to a first plasma. The first plasma is generated from first gases that include nitrogen gas, hydrogen gas, and fluorine gas. The method includes exposing, in a second plasma step executed in the plasma chamber, the film stack to a second plasma. The second plasma is generated from second gases comprising fluorine gas and oxygen gas. The second plasma selectively etches the silicon layers.Type: ApplicationFiled: January 22, 2021Publication date: July 28, 2022Inventors: Pingshan Luan, Christopher Catano, Aelan Mosden
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Patent number: 11133194Abstract: A method of etching a substrate includes generating plasma comprising a first concentration of an etchant and a second concentration of an inhibitor and etching the substrate by exposing an exposed interface between a first material and a second material to the plasma. The first material includes a lower reactivity to both the etchant and the inhibitor than the second material. The first concentration is less than the second concentration. Etching the substrate includes etching the first material and the second material at the exposed interface to form an etched indentation including an enriched region of the second material, forming a passivation layer at the enriched region using the inhibitor, and etching the first material at the etched indentation. The passivation layer reduces an etch rate of the second material to a reduced rate that is less than an etch rate of the first material.Type: GrantFiled: February 20, 2020Date of Patent: September 28, 2021Assignee: Tokyo Electron LimitedInventors: Sergey Voronin, Christopher Catano, Nicholas Joy, Alok Ranjan, Christopher Talone
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Patent number: 10903077Abstract: Embodiments are described herein that form silicon germanium nano-wires while reducing or eliminating erosion of nitride layers (e.g., masks and spacers) caused during selective etching of silicon with respect to silicon germanium during formation of silicon germanium nano-wires. oxide layers are used to protect nitride layers during formation of silicon germanium (SiGe) nano-wires. In particular, multilayer spacers including oxide/nitride/oxide layers are formed to protect the nitride layers during selective silicon etch processes that are used to form silicon germanium nano-wires, for example, for field effect transistors (FETs). The multilayer spacers allow for target levels of erosion to be achieved for the nitride layers.Type: GrantFiled: July 15, 2019Date of Patent: January 26, 2021Assignee: TOKYO ELECTRON LIMITEDInventors: Yusuke Yoshida, Christopher Catano, Christopher Talone, Nicholas Joy, Sergey Voronin
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Publication number: 20200273992Abstract: Residue at the base of a feature in a substrate to be etched is limited so that improved profiles may be obtained when forming vertical, narrow pitch, high aspect ratio features, for example fin field effect transistor (FinFET) gates. A thin bottom layer of the feature is formed of a different material than the main layer of the feature. The bottom material may be comprised of a material that preferentially etches and/or preferentially oxidizes as compared to the main layer. The bottom layer may comprise silicon germanium. The preferential etching characteristics may provide a process in which un-etched residuals do not remain. Even if residuals remain, after etch of the feature, an oxidation process may be performed. Enhanced oxidation rates of the bottom material allow any remaining residual to be oxidized. Plasma oxidation may be used. The oxidized material may then be removed by utilizing standard oxide removal mechanisms.Type: ApplicationFiled: February 5, 2020Publication date: August 27, 2020Inventors: Sergey Voronin, Christopher Catano, Sang Cheol Han, Shyam Sridhar, Yusuke Yoshida, Christopher Talone, Alok Ranjan
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Publication number: 20200266070Abstract: A method of etching a substrate includes generating plasma comprising a first concentration of an etchant and a second concentration of an inhibitor and etching the substrate by exposing an exposed interface between a first material and a second material to the plasma. The first material includes a lower reactivity to both the etchant and the inhibitor than the second material. The first concentration is less than the second concentration. Etching the substrate includes etching the first material and the second material at the exposed interface to form an etched indentation including an enriched region of the second material, forming a passivation layer at the enriched region using the inhibitor, and etching the first material at the etched indentation. The passivation layer reduces an etch rate of the second material to a reduced rate that is less than an etch rate of the first material.Type: ApplicationFiled: February 20, 2020Publication date: August 20, 2020Inventors: Sergey Voronin, Christopher Catano, Nicholas Joy, Alok Ranjan, Christopher Talone
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Publication number: 20200027736Abstract: Embodiments are described herein that form silicon germanium nano-wires while reducing or eliminating erosion of nitride layers (e.g., masks and spacers) caused during selective etching of silicon with respect to silicon germanium during formation of silicon germanium nano-wires. oxide layers are used to protect nitride layers during formation of silicon germanium (SiGe) nano-wires. In particular, multilayer spacers including oxide/nitride/oxide layers are formed to protect the nitride layers during selective silicon etch processes that are used to form silicon germanium nano-wires, for example, for field effect transistors (FETs). The multilayer spacers allow for target levels of erosion to be achieved for the nitride layers.Type: ApplicationFiled: July 15, 2019Publication date: January 23, 2020Inventors: Yusuke Yoshida, Christopher Catano, Christopher Talone, Nicholas Joy, Sergey Voronin