Abstract: At least one instruction storage coupled with a fetch unit including sets of fetch circuitry each having a same plurality of pipeline stages. The sets of fetch circuitry perform fetch operations to fetch blocks of instructions from the at least one instruction storage. Stall circuitry, in response to an indication of a hazard for a given pipeline stage of a first set of fetch circuitry, retains a fetch operation for a first block of instructions at the given pipeline stage, and zero or more fetch operations for zero or more corresponding blocks of instructions at zero or more preceding pipeline stages of the first set of fetch circuitry, until the hazard has been removed. The stall circuitry advances a fetch operation for a second block of instructions from the given pipeline stage of a second set of fetch circuitry, during an initial cycle of the one or more cycles.

Abstract: Methods and apparatus relating to a short forward branch predictor are described. In an embodiment, a processor includes a Short Forward Branch (SFB) predictor to process one or more short forward branches. The processor also includes main branch predictor logic circuitry to process one or more long forward branches. The one or more short forward branches jump forward a shorter distance than the long forward branches. Other embodiments are also disclosed and claimed.

Abstract: Examples include techniques to support fine-grained thread modes in a processor core. The examples include use of circuitry located at or with a front-end unit of a processor core's instruction execution pipeline circuitry. The circuitry receives an indication of whether the front-end unit is to be configured for a single thread or for multiple threads in order to process branch predictions, instruction cache lookups and instruction decoding for the single thread or for the multiple threads. The circuitry can then cause hardware resources of the front-end unit to be partitioned based on the received indication.

Abstract: First and second instruction storage are coupled with a fetch unit including sets of fetch circuitry each spanning a plurality of pipeline stages. A first set of fetch circuitry is to initiates a fetch operation for a block of instructions, and has an indication to read the block of instructions from the second instruction storage. The first set retains the fetch operation for the block of instructions at a pipeline stage of the plurality, for one or more cycles, until a hazard corresponding to the pipeline stage of the first set of fetch circuitry has been removed. The first set stores the block of instructions from the second instruction storage to the first instruction storage, during the one or more cycles. The first set reads the block of instructions from the first instruction storage, for the fetch operation, once the hazard has been removed.

Abstract: At least one instruction storage coupled with a fetch unit including sets of fetch circuitry each having a same plurality of pipeline stages. The sets of fetch circuitry perform fetch operations to fetch blocks of instructions from the at least one instruction storage. Stall circuitry, in response to an indication of a hazard for a given pipeline stage of a first set of fetch circuitry, retains a fetch operation for a first block of instructions at the given pipeline stage, and zero or more fetch operations for zero or more corresponding blocks of instructions at zero or more preceding pipeline stages of the first set of fetch circuitry, until the hazard has been removed. The stall circuitry advances a fetch operation for a second block of instructions from the given pipeline stage of a second set of fetch circuitry, during an initial cycle of the one or more cycles.